Apparatus and method for power continuity testing in a parallel testing system
AssigneeIntel Corporation
InventorJames E. Neeb
Life of this patent
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Abstract
Multiple devices can be tested simultaneously for power continuity or for other power performance characteristic(s). If any of the devices have short circuit defects, for example, the fuse devices connected between these defective devices and a single power supply restrict the amount of current drawn by the defective devices. This allows power continuity testing to continue for all of the other devices. At the same time, the reduced voltage level of the defective devices, caused by the restriction of current by their corresponding fuse device, can be detected by the voltage measurement device. The reduced voltage levels allow the defective devices to be identified by a test control apparatus and to be excluded from subsequent testing.
Claims20
An apparatus, comprising:
- a single power supply;
- a plurality of fuse devices coupleable between the single power supply and input terminals of respective devices under test (DUTs), each of the fuse devices being capable to reduce current flow from the single power supply to their respective DUT if that DUT is defective;
- and
- a measurement device coupleable to the input terminals of each of the DUTs to detect an electrical characteristic associated with current flow into each of the DUTs and to provide the detected electrical characteristics to identify a defective DUT.
A system, comprising:
- an automated platform to support devices under test (DUTs);
- a single power supply;
- a plurality of fuse devices coupleable between the single power supply and input terminals of respective DUTs, each of the fuse devices being capable to reduce current flow from the single power supply to their respective DUT if that DUT is defective;
- and
- a measurement device coupleable to the input terminals of each of the DUTs to detect an electrical characteristic associated with current flow into each of the DUTs and to provide the detected electrical characteristics to identify a defective DUT.
A method, comprising:
- providing current flow from a single power supply into input terminals of each of a plurality of devices under test (DUTs);
- reducing subsequent current flow into one of the DUTs if the current flow into that DUT exceeds a threshold, and allowing current to flow into at least one of the other DUTs while the current flow into the one of the DUTs is reduced;
- and
- detecting an electrical characteristic associated with the reduced current flow and using the detected electrical characteristic to identify the one of the DUTs.
A machine-readable medium having stored thereon instructions, which if executed by a processor, cause the processor to effect the following, comprising:
- control a single power supply to provide current flow into input terminals of each of a plurality of devices under test (DUTs);
- control a measurement device to detect an electrical characteristic associated with a reduced current flow into one of the DUTs if the current flow into that DUT exceeds a threshold, and control the single power supply to continue providing current flow into another DUT while the current flow into the one of the DUTs is reduced;
- and
- use information associated with the detected electrical characteristic to identify the one of the DUTs.
Dependencies are inferred from the claim text.