Non-volatile memory with a serial transistor structure with isolated well and method of operation

A non-volatile memory array comprising:

• a first memory cell within a first well;
• a second memory cell within a second well which is separated from the first well by an isolation region, the second memory cell being connected to the first memory cell by a word line;
• a third memory cell serially connected to the first memory cell;
• and
• a fourth memory cell serially connected to the second memory cell.

A semiconductor device having an electrically erasable programmable read only memory (EEPROM) array of memory cells comprising:

• a first p-well region within a semiconductor substrate;
• a second p-well region within the semiconductor substrate, wherein the second p-well region is spaced apart and electrically isolated from the first p-well region;
• a first column of memory cells within the first p-well region;
• a second column of memory cells within the second p-well region;
• a first bit line comprising a first conductor electrically connecting a first current electrode of a first transistor in the first column of memory cells and a second conductor electrically connecting a second current electrode of another transistor in the first column of memory cells;
• and
• a second bit line comprising a third conductor electrically connecting a first current electrode of a first transistor in the second column of memory cells and a fourth conductor electrically connecting a second current electrode of another transistor in the second column of memory cells.

A semiconductor device comprising:

• a semiconductor substrate;
• a first well within the semiconductor substrate, wherein the first well has a first conductivity type;
• a second well and a third well, wherein:
• the second and third wells are separated by an isolation structure;
• the second and third wells are within the first well;
• and
• the second and third wells are doped a second conductivity type that is different than the first conductivity type;
• a first memory cell overlying the second well;
• a second memory cell overlying the third well;
• a first word line electrically coupling the first memory cell and the second memory cell;
• a third memory cell overlying the second well;
• and
• a first bit line connecting the third memory cell and the first memory cell in series.

A method for programming a non-volatile memory array comprising:

• selecting a predetermined memory cell wherein:
• the predetermined memory cell is electrically connected in series to a first memory cell within a first well;
• and
• the predetermined memory cell is isolated from a second memory cell within a second well;
• biasing a first bit line connected to the predetermined memory cell with a first voltage;
• and
• biasing a first word line connected to the predetermined memory cell with a second voltage, wherein the second voltage is opposite in sign compared to the first voltage.

A method of programming a non-volatile memory array comprising:

• selecting a first memory cell within a plurality of serially connected memory cells comprising:
• applying a first voltage to a bit line electrically coupled to the first memory cell;
• and
• applying a second voltage a to word line electrically coupled to the first memory cell, wherein the second voltage is opposite in polarity compared to the first voltage;
• deselecting a second memory cell comprising:
• applying a third voltage to a bit line electrically coupled to the second memory cell, wherein the third voltage is different than the first voltage;
• and
• applying a fourth voltage to a word line electrically coupled to the second memory cell, wherein the fourth voltage is different than the second voltage.