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US 2002/0154726 A1Published application
Timer control circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakashi Miyake, Kazuyuki Iwaguro
Life of this patent
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Abstract
The timer control circuit includes plurality of timers that perform predetermined count operations. The signal selection circuit section allows to selectively pass underflow signals supplied from the timers based on the control signals. The flip-flop is supplied with an output of the signal selection circuit section a toggle signal.
Claims12
A timer control circuit comprising:
- a plurality of timers, each timer performs a counting operation and outputs a predetermined signal when the counting is over;
- a logic unit which receives a control signal and the predetermined signals from all of said timers, and based on the control signal passes one of the predetermined signals as a toggle signal;
- and
- a control unit which receives the toggle signal from said logic unit, wherein said control unit changes own output state based on the input timing of the toggle signal.
1 more element
A timer control circuit comprising:
- a plurality of timers, each timer performs a counting operation, generates and outputs an enable signal during the counting operation, and outputs a predetermined signal when the counting is over;
- a plurality of logic units which commonly receive a predetermined signal output from one of said timers and an enable signal output from at least one of said timers, each logic unit receives a control signal and the predetermined signals from some of said timers and based on the control signal passes one of the predetermined signals as a toggle signal during an effective interval of the enable signal(s) and
- a plurality of control units, each control unit receives the toggle signal from corresponding one of said logic units, wherein each control unit changes its output state based on the input timing of the toggle signal.
Dependencies are inferred from the claim text.