Image processing apparatus and method for displaying picture-in-picture with frame rate conversion

An image processing apparatus for displaying on one display device a plurality of input data asynchronously input through different channels and converting frame rates of the input data in accordance with an output frame rate of the display device, the apparatus comprising:

• an input buffer unit for buffering input data which are externally and asynchronously input through at least two channels by different input clock signals and outputting buffered data as first data and first data enabling signals;
• a data synchronizing unit for synchronizing the first data output from the input buffer unit with an output clock signal in response to the input clock signals and the first data enabling signals and outputting synchronized data as second data and second data enabling signals in response to each of the first data enabling signals;
• a first memory for multiplexing the second data according to time sharing, storing the second data in different regions, and outputting the stored data in response to a first memory enabling signal;
• a second memory for writing and reading data output from the first memory in response to a frame buffer control signal;
• a third memory for storing data output from the second memory and outputting the stored data as a display signal in response to a second memory enabling signal;
• and
• a memory control unit for generating the first memory enabling signal to control data flow between the first memory and the second memory, generating the frame buffer control signal to control frame rates of the first and second input data and the display signal, and generating the second memory enabling signal to control data flow between the second memory and the third memory.