Method and apparatus for implementing low latency crossbar switches with integrated storage signals

A computer system, comprising:

• a crossbar switch comprising:
• a plurality of ports coupled to a bus;
• at least one memory element coupled to one of said plurality of ports;
• and
• a circuit for generating a write enable pulse coupled to each of said at least one memory element, comprising:
• a pulse generator for generating a pulse, said pulse tracking a leading edge of a clock signal;
• a write enable signal generator for generating a write enable signal;
• and
• a first logic circuit coupled to said pulse generator and said write enable signal generator for generating said write enable pulse by combining said pulse and said write enable signal;
• and
• at least one processing unit coupled to each of said plurality of port.

A method for communicating between a first processing unit coupled to a first port of a crossbar switch and a second processing unit coupled to a second port of said crossbar switch, comprising:

• generating a request for a communication path from said first processor to said second processor;
• transmitting data from said second processor to said first port;
• storing said data in a memory element in said first port, comprising:
• generating a pulse in response to a clock signal, said pulse tracking a leading edge of said clock signal;
• generating a write enable signal;
• and
• generating a write enable pulse by combining said pulse and said write enable signal;
• and
• reading said data from said memory element.