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US 2002/0154566 A1Published application
Sending signal through integrated circuit during setup time
AssigneeMicron Technology, Inc.
InventorsDonald M. Morgan, Todd A. Merritt
Life of this patent
Estimating the term…
Abstract
A memory having a control circuit for initiating a read or a write operation in response to a combination of input signals during a setup time is described. The setup time is a specified time period during which all inputs must remain valid before a next appearance of a rising edge of a clock signal. The control circuit uses the setup time to send a signal from one part of the memory to another part of the memory to avoid the propagation delay time. Further, a circuit is provided which prepares the memory for a write operation prior to the setup time.
Claims47
A memory device comprising:
- a memory area;
- and
- a control circuit connected to the memory area for initiating a memory operation based on a combination of input signals during a setup time to access the memory area during the setup time, wherein the setup time occurs before the combination of input signals is validated for the memory operation.
A memory device, comprising:
- a plurality of memory cells;
- a first circuit for receiving a plurality of control signals to generate an enable signal indicating whether a combination of the control signals is valid for a memory access operation;
- and
- a second circuit connected to the memory cells and the first circuit for receiving the control signals to generate a setup signal for initiating the memory access operation during a setup time and before the enable signal indicates the combination of the control signals is valid for a memory access operation
1 more element
A memory device, comprising:
- a plurality of inputs for receiving a first set of input signals and a second set of input signals;
- a memory area having a plurality memory cells;
- and
- a setup time write circuit connected to the inputs and the memory area, the setup time write circuit including:
- an input circuit for generating an enable signal based on the first set of input signals;
- and
- an output circuit for generating an output signal based on the second set of input signals to activate a write operation during the setup time and before the enable signal validates a combination of input signals of the first set of input signals is valid for the write operation.
4 more elements
A memory device, comprising:
- a memory area including a first memory array, an intermediate memory array, and a last memory array, the last memory array being located farthest from the first memory array;
- a data driver connected to the memory area;
- and
- a control circuit connected to the data driver for enabling data from the data driver to propagate to the memory area in a direction from the first memory array to the last memory array during a setup time.
1 more element
A memory device, comprising:
- a memory portion including a first memory array, an intermediate memory array, and a last memory array, the last memory array being located farthest from the first memory array;
- a data write driver connected to the memory portion and located near the first memory array;
- a data write line connected to the data write driver, the first memory array and the last memory array;
- and
- a control circuit located near the last memory array and connected to the data write driver for enabling data from the data write driver to propagate to the memory portion via the data write line in the direction from the first memory array to the last memory array in a write operation anticipated during a setup time.
2 more elements
An integrated circuit die comprising:
- a first circuit region;
- a memory region connected to the first circuit region;
- a second circuit region connected to memory region and the first circuit region;
- a data driver located in the first circuit region for receiving data;
- and
- a control circuit located in the second circuit region for generating a setup signal during a setup time to enable the data to propagate from the first region to the memory region during the setup time.
3 more elements
A system comprising:
- a processor;
- and
- a dynamic memory device connected to the processor, the memory device including:
- a memory area;
- and
- a control circuit connected to the memory area for initiating a memory operation based on a combination of input signals during a setup time to access the memory area during the setup time, wherein the setup time occurs before the combination of input signals is validated for the memory operation.
3 more elements
A system comprising:
- a processor;
- and
- a static memory device connected to the processor, the memory device including:
- a memory area;
- and
- a control circuit connected to the memory area for initiating a memory operation based on a combination of input signals during a setup time to access the memory area during the setup time, wherein the setup time occurs before the combination of input signals is validated for the memory operation.
3 more elements
A system comprising:
- a processor;
- and
- a dynamic memory device connected to the processor, the memory device including:
- a plurality of memory cells;
- a first circuit for receiving a plurality of control signals to generate an enable signal indicating whether a combination of the control signals is valid for a memory access operation;
- and
- a second circuit connected to the memory cells and the first circuit for receiving the control signals to generate a setup signal for initiating the memory access operation during a setup time and before the enable signal indicates the combination of the control signals is valid for a memory access operation
4 more elements
A system comprising:
- a processor;
- and
- a static memory device connected to the processor, the memory device including:
- a plurality of memory cells;
- a first circuit for receiving a plurality of control signals to generate an enable signal indicating whether a combination of the control signals is valid for a memory access operation;
- and
- a second circuit connected to the memory cells and the first circuit for receiving the control signals to generate a setup signal for initiating the memory access operation during a setup time and before the enable signal indicates the combination of the control signals is valid for a memory access operation
4 more elements
A system comprising:
- a processor;
- and
- a dynamic memory device connected to the processor, the memory device including:
- a plurality of inputs for receiving a first set of input signals and a second set of input signals;
- a memory area having a plurality memory cells;
- and
- a setup time write circuit connected to the inputs and the memory area, the setup time write circuit including:
- an input circuit for generating an enable signal based on the first set of input signals;
- and
- an output circuit for generating an output signal based on the second set of input signals to activate a write operation during the setup time and before the enable signal validates a combination of input signals of the first set of input signals is valid for the write operation.
7 more elements
A system comprising:
- a processor;
- and
- a static memory device connected to the processor, the memory device including:
- a plurality of inputs for receiving a first set of input signals and a second set of input signals;
- a memory area having a plurality memory cells;
- and
- a setup time write circuit connected to the inputs and the memory area, the setup time write circuit including:
- an input circuit for generating an enable signal based on the first set of input signals;
- and
- an output circuit for generating an output signal based on the second set of input signals to activate a write operation during the setup time and before the enable signal validates a combination of input signals of the first set of input signals is valid for the write operation.
7 more elements
A system comprising:
- a processor;
- and
- a dynamic memory device connected to the processor, the memory device including:
- a memory area including a first memory array, an intermediate memory array, and a last memory array, the last memory array being located farthest from the first memory array;
- a data driver connected to the memory area;
- and
- a control circuit connected to the data driver for enabling data from the data driver to propagate to the memory area in a direction from the first memory array to the last memory array during a setup time.
4 more elements
, A system comprising:
- a processor;
- and
- a static memory device connected to the processor, the memory device including:
- a memory area including a first memory array, an intermediate memory array, and a last memory array, the last memory array being located farthest from the first memory array;
- a data driver connected to the memory area;
- and
- a control circuit connected to the data driver for enabling data from the data driver to propagate to the memory area in a direction from the first memory array to the last memory array during a setup time.
4 more elements
The system of claim 33, wherein the first memory array and the last memory array line up in a column.
The system of claim 33, wherein the control circuit includes:
- an input circuit for receiving a plurality of control signals to generate an enable signal indicating whether a combination of the control signals is valid for a memory access operation;
- and
- an output circuit connected to the first circuit for receiving the control signals to generate a setup signal for initiating the memory access operation during a setup time and before the enable signal indicates the combination of the control signals is valid for a memory access operation.
A system comprising:
- a processor;
- and
- a dynamic memory device connected to the processor, the memory device including:
- a memory portion including a first memory array, an intermediate memory array, and a last memory array, the last memory array being located farthest from the first memory array;
- a data write driver connected to the memory portion and located near the first memory array;
- a data write line connected to the data write driver, the first memory array and the last memory array;
- and
- a control circuit located near the last memory array and connected to the data write driver for enabling data from the data write driver to propagate to the memory portion via the data write line in the direction from the first memory array to the last memory array in a write operation anticipated during a setup time.
5 more elements
A system comprising:
- a processor;
- and
- a static memory device connected to the processor, the memory device including:
- a memory portion including a first memory array, an intermediate memory array, and a last memory array, the last memory array being located farthest from the first memory array;
- a data write driver connected to the memory portion and located near the first memory array;
- a data write line connected to the data write driver, the first memory array and the last memory array;
- and
- a control circuit located near the last memory array and connected to the data write driver for enabling data from the data write driver to propagate to the memory portion via the data write line in the direction from the first memory array to the last memory array in a write operation anticipated during a setup time.
5 more elements
, A system comprising:
- a processor;
- and
- a dynamic memory device connected to the processor, the memory device including:
- a first circuit region;
- a memory region connected to the first circuit region;
- a second circuit region connected to memory region and the first circuit region;
- a data driver located in the first circuit region for receiving data;
- and
- a control circuit located in the second circuit region for generating a setup signal during a setup time to enable the data to propagate from the first region to the memory region during the setup time.
6 more elements
The system of claim 40 further comprising a plurality of memory arrays located in the memory region and lining up in a column, the column being extended in a direction from first circuit region to the second circuit region.
A system comprising:
- a processor;
- and
- a static memory device connected to the processor, the memory device including:
- a first circuit region;
- a memory region connected to the first circuit region;
- a second circuit region connected to memory region and the first circuit region;
- a data driver located in the first circuit region for receiving data;
- and
- a control circuit located in the second circuit region for generating a setup signal during a setup time to enable the data to propagate from the first region to the memory region during the setup time.
6 more elements
A method of operating a memory device, the method comprising:
- receiving a combination of input signals;
- and
- initiating a memory operation during a setup time and before the combination of the input signals is validated for the memory operation,
Dependencies are inferred from the claim text.