Semiconductor integrated circuit device

A semiconductor integrated circuit device having a semiconductor memory circuit incorporated therein, comprising:

• memory cell arrays each provided with a plurality of static memory cells at points where a plurality of word lines and a plurality of complementary bit line pairs intersect;
• precharge circuits which respectively precharge said complementary bit line pairs by a source voltage;
• pre-amplifiers each of which receives a signal of a memory cell, which is read into each of said complementary bit line pairs;
• and
• main amplifiers each of which receives a signal outputted from said each pre-amplifier,
• wherein the number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into said each complementary bit line pair, which is supplied to the input of said each pre-amplifier, becomes greater than that of a signal outputted from said pre-amplifier during a period of from the selection of said each word line to the start of the operation of said each main amplifier.