Sense amplifier for reduction of access device leakage

A sense amplifier circuit, comprising:

• an N-sense amplifier circuit having a first node and a second node;
• a P-sense amplifier circuit having a first node and a second node;
• a first P-channel transistor coupled between the first node of the N-sense amplifier circuit and the first node of the P-sense amplifier circuit;
• and
• a second P-channel transistor coupled between the second node of the N-sense amplifier circuit and the second node of the P-sense amplifier circuit.

A sense amplifier circuit, comprising:

• an N-sense amplifier circuit having a first node and a second node;
• a P-sense amplifier circuit having a first node and a second node, the nodes of the P-sense amplifier circuit being coupled to a complementary pair of digit lines;
• a first P-channel transistor which selectively couples the first node of the P-sense amplifier circuit to the first node of the N-sense amplifier circuit;
• and
• a second P-channel transistor which selectively couples the second node of the P-sense amplifier circuit to the second node of the N-sense amplifier circuit.

A memory circuit, comprising:

• a memory array, the memory array having multiple rows of word lines and multiple columns of digit lines, wherein intersections of the multiple rows of word lines and the multiple columns of digit lines comprises multiple memory cells;
• and
• a sense amplifier circuit coupled to the memory array, the sense amplifier circuit including multiple sense amplifiers, each sense amplifier comprising:
• a first amplifier having a first node and a second node, the first amplifier including a pair of cross-coupled transistors of a first channel type;
• a second amplifier having a first node and a second node, the second amplifier including a pair of cross-coupled transistors of a second channel type, the nodes of the second amplifier coupled to a complementary pair of the digit lines;
• a third transistor of the second channel type coupled between the first node of the first amplifier and the first node of the second amplifier;
• and
• a fourth transistor of the second channel type coupled between the second node of the first amplifier and the second node of the second amplifier.

A dynamic random access memory (DRAM) circuit, comprising:

• a DRAM memory array having multiple rows of word lines and multiple columns of digit lines, wherein intersections of the multiple rows of word lines and the multiple columns of digit lines comprises multiple DRAM memory cells;
• and
• a sense amplifier circuit coupled to the memory array, the sense amplifier circuit including multiple sense amplifiers, each sense amplifier comprising:
• an N-sense amplifier circuit having a first node and a second node;
• a P-sense amplifier circuit having a first node and a second node;
• a first P-channel transistor coupled between the first node of the N-sense amplifier circuit and the first node of the P-sense amplifier circuit;
• and
• a second P-channel transistor coupled between the second node of the N-sense amplifier circuit and the second node of the P-sense amplifier circuit.

An electronic system, comprising:

• a central processing unit (CPU);
• a memory device, the memory device comprising:
• a memory array having multiple rows of word lines and multiple columns of digit lines, wherein intersections of the multiple rows of word lines and the multiple columns of digit lines comprises multiple memory cells;
• and
• a sense amplifier circuit, coupled to the memory array, including multiple sense amplifiers, each sense amplifier comprising:
• a first amplifier having a first node and a second node, and including a pair of cross-coupled transistors of a first channel type;
• a second amplifier having a first node and a second node, and including a pair of cross-coupled transistors of a second channel type, the nodes of the second amplifier being coupled to a complementary pair of the digit lines;
• a third transistor of the second channel type coupled between the first node of the first amplifier and the first node of the second amplifier;
• and
• a fourth transistor of the second channel type coupled between the second node of the first amplifier and the second node of the second amplifier;
• and
• a system bus for communicatively coupling the CPU and the memory device.

A method of forming a sense amplifier circuit, comprising:

• forming an N-sense amplifier having first and second nodes;
• forming a P-sense amplifier having first and second nodes;
• forming a first P-channel transistor between the first nodes of the N-sense and P-sense amplifiers;
• and
• forming a second P-channel transistor between the second nodes of the N-sense and P-sense amplifiers.

A method of forming a sense amplifier circuit, comprising:

• forming a pair of cross-coupled N-channel transistors;
• forming a first pair of P-channel transistors;
• and
• forming a second pair of P-channel transistors, the second pair of P-channel transistors being formed between the pair of N-channel transistors and the first pair of P-channel transistors.

A method of sensing a memory cell in a memory circuit, comprising:

• accessing a memory cell to generate a differential voltage signal across a pair of complementary digit lines;
• and
• sensing the differential voltage signal using a sense amplifier circuit which includes a first sense amplifier of a first channel type and a second sense amplifier of a second channel type, wherein the sensing includes:
• firing the first sense amplifier to move a first one of the digit lines towards a predetermined potential;
• and
• limiting the movement of the first one of the digit lines to prevent the first one of the digit lines from reaching the predetermined potential.

A method of sensing a memory cell in a memory circuit, comprising:

• accessing a memory cell to generate a differential voltage signal across a pair of complementary digit lines, the pair of complementary digit lines including a low voltage digit line and a high voltage digit line;
• and
• sensing the differential voltage signal using a sense amplifier circuit which includes an N-sense amplifier and a P-sense amplifier, wherein the sensing includes:
• firing the N-sense amplifier to discharge the low voltage digit line towards ground;
• and
• limiting the discharge of the low voltage digit line to prevent the low voltage digit line from reaching ground.