System and method for redundancy implementation in a semiconductor device
AssigneeVirage Logic Corporation
InventorsAlex Shubat, Chang Hee Hong
Life of this patent
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Abstract
A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box register is provided outside the memory macro cell associated with the memory instance. The fuse box register is operable to store location information pertaining to a faulty portion in the prime memory array. A redundancy scan storage element in the memory instance is operable to receive the location information from the fuse box register, which location information is used for replacing at least a part of the faulty portion in the prime memory array with at least a part of the redundant portion.
Claims1
An integrated semiconductor device, comprising:
- a plurality of memory instances embedded in said integrated semiconductor device's circuitry, wherein at least one of said plurality of memory instances comprises a prime memory array and a redundant memory portion;
- a volatile scan register disposed in said at least one of said plurality of memory instances, said volatile scan register including a plurality of concatenated flip-flops;
- a fuse box register disposed external to said plurality of memory instances in a selected area of said integrated semiconductor device, said fuse box register including a plurality of fuses for storing fuse information, each fuse being in either an open or closed state, wherein said fuse information is associated with location data pertaining to a faulty portion in said prime memory array;
- and
- means for transferring said fuse information to said volatile scan register from said fuse box register upon a reset of said integrated semiconductor device,
- wherein said fuse information in said volatile scan register is used for replacing said faulty portion in said prime memory array with at least a part of said redundant memory portion.
Dependencies are inferred from the claim text.