Method and apparatus for generating and controlling integrated circuit memory write signals
AssigneesSun Microsystems, Inc., LSI Logic Corporation
InventorsJames Ma, Mark Kawahigashi
Life of this patent
Estimating the term…
Abstract
A circuit and method for generating a write enable pulse that is independent of the clock duty cycle and the clock frequency. The circuit includes a pulse generator for generating a pulse in response to a clock signal and a write enable signal generator for generating a write enable pulse. The pulse tracks the leading edge of the clock signal. A logic circuit is coupled to the pulse generator and the write enable signal generator to generate the write enable pulse by combining the pulse and the write enable signal.
Claims18
A circuit for generating a write enable pulse, comprising:
- a pulse generator for generating a pulse, the pulse tracking a leading edge of a clock signal;
- a write enable signal generator for generating a write enable signal;
- and
- a first logic circuit coupled to the pulse generator and the write enable signal generator for generating the write enable pulse by combing the pulse and the write enable signal.
A method for generating a write enable pulse, comprising:
- generating a pulse in response to a clock signal, the pulse tracking the leading edge of the clock signal;
- generating a write enable signal;
- generating the write enable pulse by combining the pulse and the write enable signal.
A memory circuit, comprising:
- a plurality of memory cells, each of the plurality of memory cells being coupled to a bit line and a word line;
- a write logic circuit coupled to the plurality of memory cells, the write logic circuit providing a data signal to the bit line in response to a write enable pulse, the data signal corresponding to input data;
- and
- a write enable pulse generator coupled to the write logic circuit, the write enable pulse generator comprising:
- a pulse generator for generating a pulse in response to a clock signal, the pulse tracking a leading edge of the clock signal;
- a write enable signal generator for generating a write enable signal;
- and
- a logic circuit coupled to the pulse generator and the write enable signal generator for generating a write enable pulse by combining the pulse and the write enable signal.
Dependencies are inferred from the claim text.