Bus driving circuit and memory device having same
AssigneeKabushiki Kaisha Toshiba
InventorYukihiro Fujimoto
Life of this patent
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Abstract
A bus driving circuit comprises: a bus pre-charge part for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the but line on the basis of the potential of the bus line and data inputted from a pre-charge type circuit when the enable signal is in an active state. Thus, it is possible to inhibit the influence of the coupling noises between bus lines, and it is possible to rapidly transfer data.
Claims16
A bus driving circuit comprising:
- bus pre-charge means for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal;
- a tristate buffer for driving said bus line on the basis of a gate control signal;
- and
- a gate control circuit for transmitting said gate control signal to said tristate buffer so as not to drive said bus line when an enable signal is in an inactive state, and for transmitting said gate control signal to said tristate buffer so as to drive said but line on the basis of the potential of said bus line and data inputted from a pre-charge type circuit when said enable signal is in an active state.
A memory unit comprising:
- a plurality of memory cells arranged in the form of a matrix;
- word lines for selecting memory cells on the same line;
- bit lines for transmitting the potential levels of the memory cells selected by said word lines;
- a bit line pre-charge circuit for pre-charging said bit lines;
- a sense amplifier circuit for amplifying the potentials of the memory cells which are read to said bit lines;
- bus pre-charge means for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal;
- a tristate buffer for driving said bus line on the basis of a gate control signal;
- and
- a gate control circuit for transmitting said gate control signal to said tristate buffer so as not to drive said bus line when an enable signal is in an inactive state, and for transmitting said gate control signal to said tristate buffer so as to drive said bus line on the basis of the potential of said bus line and the output data of said sense amplifier circuit when said enable signal is in an active state.
Dependencies are inferred from the claim text.