Non-volatile, electrically alterable semiconductor memory

Method of writing a memory location of a memory comprising at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, row selection means for selecting rows among said plurality of rows, column selection means for selecting columns among said plurality of columns, a write circuit for simultaneously writing a first number of memory cells, a plurality of doped semiconductor regions extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased, a plurality of column packets each one containing a second number of columns, said second number being equal to or higher than said first number, memory cells belonging to columns of a same column packet being formed in a same doped semiconductor region distinct from the doped semiconductor regions in which memory cells belonging to columns of the other column packets are formed, the method providing for:

• selecting one row among the plurality of rows;
• selecting one column packet among the plurality of columns packet;
• and
• in the selected column packet, selecting a number of columns equal to said first number containing memory cells that are to be written simultaneously by the write circuit in such a way that the selected columns are distributed among the columns of the column packet so as to be at the substantially maximum distance from each other allowable within the column packet.