Flash memory erase method
AssigneeMacronix International Co., Ltd.
InventorsMing-Hung Chou, Hsin-Yi Ho, Smile Huang
Life of this patent
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Abstract
An flash memory erase method. A bias Vg is applied to a gate of a memory cell. A bias Vd is applied to a source/drain region of the memory cell to execute an erase operation. The bias Vd is increased from an initial value to a predetermined value over time. During the increase of the bias Vd, no inspection is performed. Whether the memory of each memory cell has been erased is inspected. If the erase operation is complete, the erase operation is over. If not, a voltage raise erase-inspection step is performed at least once until it is confirmed that the memory of all the memory cells has been erase. Each voltage raise erase-inspection step includes an erase step with a raised voltage and an inspection step afterwards.
Claims19
A flash memory erase method that comprises a plurality of memory cells, the method comprising:
- performing a first erase step, which includes applying a bias Vg to a plurality of gates of the memory cells, a bias Vd to a plurality of source/drain regions of the memory cells, wherein the bias Vd is gradually increased from an initial value to a predetermined value, and no inspection step is performed while increasing the bias Vd;
- and
- inspecting whether memory of all the memory cells is erased, and performing a second erase step when the answer is no, wherein the second erase step includes at least one voltage raise erase-inspection step to insure that memory of all the memory cells has been erased;
- wherein
- an ith voltage raise erase-inspection with a duration T(i) includes a voltage raise erase step and an inspection step afterwards, and the first voltage raise erase step has a value of Vd larger than the predetermined value of Vd, and when i>1, a value of the Vd at the ith voltage raise erase-inspection step is higher than that of the (i−1)th voltage raise erase-inspection step.
A flash memory erase method, wherein the flash memory comprises a plurality of memory cells, the method comprising:
- performing a first erase step to allow a potential difference ΔV between a gate and a source/drain region of each of the memory cells, wherein the potential difference ΔV starts from an initial value and gradually increases up to a predetermined value, and while increasing the potential difference ΔV, no inspection step is performed;
- inspecting whether memory of all the memory cells has been erased, and performing a second erase step if the memory of any of the memory cells is not erased, wherein the second erase step comprises i episodes of voltage raise erase-inspection steps to insure the memory of all the memory cells has been erased, and i≧1;
- wherein
- the ith voltage raise erase-inspection step comprises a voltage raise erase step lasting for a time period T(i) and an inspection step afterwards, the first voltage raise erase step has the potential difference ΔV higher than the predetermined value, and when i>1, the ΔV is higher than that of the voltage raise erase step for i−1.
Dependencies are inferred from the claim text.