Pulsed write techniques for magneto-resistive memories

A magneto-resistive storage device comprising:

• a magneto-resistive bit having a first end and a second end;
• a word line extending adjacent the magneto-resistive bit, the word line connected to the first end of the magneto-resistive bit;
• word line current providing means for selectively providing a word line current to the word line;
• switching means coupled to the second end of the magneto-resistive bit for selectively providing a path for a read or a write sense current to flow from the word line, through at least part of the magneto-resistive bit, and to a predetermined voltage terminal;
• reading means coupled to the word line for providing a path for the read sense current to flow to the word line, the reading means reading the resistive state of the magneto-resistive bit via the read sense current;
• and
• controller means for controlling the word line current providing means, the switching means, and the reading means;
• the controller means performing a write of the magneto-resistive bit by enabling the word line current providing means to provide a word line current to the word line, enabling the switching means to provide a path for the write sense current to flow from the word line, through at least part of the magneto-resistive bit, and to the predetermined voltage terminal, and disabling the reading means to prevent the reading means from providing a path for the read sense current to flow to the word line;
• and
• the controller means performing a read of the magneto-resistive bit by disabling the word line current providing means to prevent the word line current providing means from providing a word line current to the word line, enabling the switching means to provide a path for the read sense current to flow from the word line, through at least part of the magneto-resistive bit, and to the predetermined voltage terminal, and enabling the reading means to provide a path for the read sense current to flow to the word line and to read the resistive state of the magneto-resistive bit via the read sense current.

A method for operating a magneto-resistive storage device, the magneto-resistive storage device having a magneto-resistive bit with a first end and a second end, a word line extending adjacent the magneto-resistive bit with the word line connected to the first end of the magneto-resistive bit, and a reading circuit coupled to the word line for providing a path for a read sense current to flow to the word line and for sensing the resistive state of the magneto-resistive bit via the read sense current, the method comprising the steps of:

• preventing the read circuit from providing a path for the read sense current to flow to the word line;
• supplying a word line current to the word line;
• and
• drawing a write sense current from the word line current through at least part of the magneto-resistive bit.

A magneto-resistive storage element comprising:

• a first magneto-resistive bit having a first end and a second end;
• a second magneto-resistive bit having a first end and a second end;
• a word line extending adjacent the first and second magneto-resistive bits such that a word line current passing through the word line provides a magnetic field component toward one end of the first magneto-resistive bit and toward the other end of the second magneto-resistive bit, the word line connected to the first end of the first magneto-resistive bit and the first end of the second magneto-resistive bit;
• and
• switching means coupled to the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit for selectively providing a path for a write sense current to flow from the word line, through at least part of the first and second magneto-resistive bits, and to a predetermined voltage terminal.

A magneto-resistive memory comprising:

• a latch circuit including a first inverter and a second inverter coupled together in a cross-coupled configuration, each of the first and second inverters having a positive supply terminal, a negative supply terminal, an input terminal and an output terminal, the positive supply terminal of the first and second inverters coupled to a power supply voltage;
• the latch circuit further including a load transistor for loading a state into the latch circuit, the load transistor having a source terminal coupled to the input terminal of the first inverter, a drain terminal coupled to the input terminal of the second inverter, and a gate terminal;
• at least one magneto-resistive memory cell having a first magneto-resistive bit with a first end and a second end, and a second magneto-resistive bit having a first end and a second end, the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit being selectively coupled to ground through one or more switching means;
• a first word line coupled to the negative supply terminal of the first inverter and extending adjacent the first magneto-resistive bit of at least one magneto-resistive memory cell, each of the first magneto-resistive bits having a first end coupled to the first word line;
• a second word line coupled to the negative supply terminal of the second inverter and extending adjacent the second magneto-resistive bit of at least one magneto-resistive memory cell, each of the second magneto-resistive bits having a first end coupled to the second word line;
• and
• a write transistor having a source terminal coupled to the first word line, a drain coupled to the second word line, and a gate coupled to a write control terminal, the write transistor for selectively connecting the first word line and the second word line depending on the state of the write control terminal.