Method and circuit for determining sense amplifier sensitivity

A dynamic random access memory circuit capable of operating in either a test mode or a normal mode, the dynamic random access memory circuit comprising:

• a first memory cell, a first characterization cell, and a second characterization cell coupled to a first bit line;
• a second memory cell, a third characterization cell, and a fourth characterization cell coupled to a second bit line;
• and
• a sense amplifier for sensing a voltage differential appearing between the first bit line and the second bit line and outputting a signal indicative of the sensed voltage differential;
• wherein during the normal mode the first memory cell is selectively enabled to transfer a first memory charge onto the first bit line and the second memory cell is selectively enabled to transfer a second memory charge onto the second bit line, and the output signal provides a logic level relating to the transferred memory charge;
• wherein during a first test mode the first characterization cell is selectively enabled to transfer a predetermined first reference charge onto the first bit line and the third characterization cell is simultaneously selectively enabled to transfer a predetermined second reference charge that is different from the first reference charge by an increment onto the second bit line, and the output signal provides information relating to a sensitivity of the sense amplifier;
• and
• wherein during a second test mode the second characterization cell is selectively enabled to transfer a predetermined third reference charge onto the first bit line and the fourth characterization cell is simultaneously selectively enabled to transfer a predetermined fourth reference charge that is different from the third reference charge by an increment onto the second bit line, and the output signal provides information relating to a sensitivity of the sense amplifier.

A memory device comprising:

• a plurality of bit line pairs, each bit line pair including an even bit line and an odd bit line;
• a plurality of memory cells, each memory cell being coupled to one of the even or the odd bit lines such that each bit line has an equal number of memory cells coupled to it;
• a plurality of sense amplifiers, each sense amplifier coupled to a corresponding one of the bit line pairs;
• an even reference supply line;
• an odd reference supply line;
• for each even bit line, at least one characterization cell coupled between the even reference supply line and the particular even bit line;
• for each odd bit line, at least one characterization cell coupled between the odd reference supply line and the particular odd bit line;
• wherein, at least during a test mode, the even reference supply line is characterized by having a distributed resistance along the even reference supply line.

A method of testing a memory device that includes a plurality of bit line pairs, each pair including an even bit line coupled to an even reference supply line by a test cell and an odd bit line coupled to an odd reference supply line by a test cell, the memory device further including a plurality of sense amplifiers, each sense amplifier coupled to a respective one of the bit line pairs, the method comprising:

• generating an even test voltage on the even reference supply line, the even test voltage being a function of physical location along the even reference supply line;
• generating an odd test voltage on the odd reference supply line;
• the odd test voltage being a function of physical location and along the odd reference line;
• and
• testing at least one of the sense amplifiers using at least one test cell coupled to the even reference supply line and at least one test cell coupled to the odd reference supply line.

A method of determining the sensitivity of a sense amplifier located within a dynamic random access memory circuit that includes first and second characterization cells and a first memory cell coupled to a first bit line, and a third and fourth characterization cells and a second memory cell coupled to a second bit line, the method comprising:

• isolating the first and second memory cells from transferring a memory charge to the first and second bit lines respectively;
• placing a first reference charge within the first characterization cell;
• placing a second reference charge within the third characterization cell, the second reference charge being different from the first reference charge;
• transferring the first reference charge from the first characterization cell to the first bit line;
• transferring the second reference charge from the second characterization cell to the second bit line;
• sensing a first voltage differential appearing between the first bit line and the second bit line;
• placing a third reference charge within the second characterization cell;
• placing a fourth reference charge within the fourth characterization cell, the fourth reference charge being different from the third reference charge;
• transferring the third reference charge from the second characterization cell to the first bit line;
• transferring the fourth reference charge from the fourth characterization cell to the second bit line;
• sensing a second voltage differential appearing between the first bit line and the second bit line;
• and
• obtaining information about the sensitivity of the sense amplifier from the first voltage differential and the second voltage differential.