Video display device
AssigneeSanyo Electric Co., Ltd.
InventorsKatuya Anzai, Ryoichi Yokoyama
Life of this patent
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Abstract
On a substrate (10), one or more inverter circuits for adjusting delay time are provided between an external clock input section (T1, T2) to which a clock signal CKH1 or CKH2 is externally input and a sampling signal generating circuit (shift register). Of the inverter circuits, only necessary inverter circuits are selected and connected, thereby delaying the sampling timing for a video signal. The connection between the inverter circuit and the signal path is achieved simply by changing a connection line pattern mask in accordance with the number of inverter circuits to be connected, and without changing other manufacturing processes.
Claims10
A display device in which a display signal externally transferred in sequence is sampled based on an external clock signal and is supplied to each of pixels arranged in a matrix for causing each pixel to perform display, said display device comprising:
- a sampling signal generating circuit for generating a sampling signal used for sampling said display signal, based on said external clock signal;
- and
- at least one clock delaying circuit disposed between said sampling signal generating circuit and a terminal for supplying said external clock signal and having a function of delaying said external clock signal,
- wherein said at least one clock delaying circuit is connected to a signal transmission line for supplying said external clock signal to said sampling signal generating circuit, said signal transmission line and a connection line connecting to said signal transmission line being formed using a pattern mask in accordance with the required number of connections for the delaying circuit in the process for forming said signal transmission line and said connection line.
A display device in which a display signal externally transferred in sequence is sampled based on an external clock signal and is supplied to each of a plurality of pixels arranged in a matrix, for causing each pixel to generate a display, said display device comprising:
- a sampling signal generating circuit for generating a sampling signal used for sampling said display signal, based on said external clock signal;
- and
- at least one clock delaying circuit disposed between said sampling signal generating circuit and a terminal for supplying said external clock signal, said at least one clock delaying circuit having a function of delaying said external clock signal,
- wherein at least one of said at least one clock delaying circuit is insulated from a signal transmission line which is provided for supplying said external signal to said sampling signal generating circuit.
A display device in which a display signal externally transferred in sequence is sampled based on an external clock signal and is supplied to each of a plurality of pixels arranged in a matrix for causing each pixel to generate a display, said display device comprising:
- a sampling signal generating circuit for generating a sampling signal used for sampling said display signal, based on said external clock signal;
- and
- at least one clock delaying circuit having a function of delaying said external clock signal, said at least one clock delaying circuit being connected with a signal transmission line between said sampling signal generating circuit and a terminal for supplying said external clock signal,
- wherein in each said clock delaying circuit so provided, a plurality of elements forming each circuit are spaced at an interval which is larger than the width of said signal transmission line.
Dependencies are inferred from the claim text.