Back to results
US 2002/0154047 A1Published application
Developing a desired output sampling rate for oversampled converters
AssigneeIntel Corporation
InventorsJeongjin Roh, Vijayakumaran V. Nair, Jiang Chen, Rose W. Wang
Life of this patent
Estimating the term…
Abstract
An analog to digital converter may achieve an output sampling rate that is not an integer multiple of the system clock. This may be done without using the conventional phase-locked loop circuit that generally requires a longer design time, more testing, and more silicon area. A pseudo clock may be generated from the system clock in which some of the system clock pulses are disabled to achieve a pseudo clock with the desired effective frequency.
Claims22
A circuit comprising:
- a clock signal generator to generate a clock signal having some pulses that toggle and other pulses that are disabled;
- and
- a delta-sigma modulator coupled to receive the clock signal.
A circuit comprising:
- a delta-sigma modulator;
- and
- a device to convert a system clock that is not an integer multiple of the converter output sampling rate to a sampling rate to achieve the output sampling rate without using a phase-locked loop.
A method comprising:
- receiving a analog signal;
- converting a system clock to a pseudo clock by disabling some of the system clock pulses;
- and
- using said pseudo clock as a clock for a delta-sigma modulator.
1 more element
Dependencies are inferred from the claim text.