Center phase verifying circuit and center phase verifying method

A phase correction circuit for correcting phase disturbance of data signal input as n-phase serial data, where n is an integer not less than 2, comprising:

• a serial to parallel conversion circuit for outputting, via a plural number of output ports, parallel data obtained on serial to parallel conversion of said data signal at a period equal to n times the period of the data signal;
• a phase comparator circuit for comparing phases of parallel data output from each of said output ports for detecting phase non-coincidence;
• a counter for counting the number of times of detection of phase non-coincidence in each of said output ports by said phase comparator circuit;
• and
• a circuit for deciding said center phase based on the counted number of times of phase non-coincidence and for converting the serial to parallel converted data signal into serial data having the correct period based on the decided center phase to output resulting serial data.

A method for deciding a center phase of data signal input as n-phase serial data, where n is an integer not less than 2, said method comprising the steps of:

• serial to parallel converting said data signal to output parallel data obtained on the serial to parallel conversion at a period equal to n times the period of the data signal via a plural number of output ports;
• comparing the phases of parallel data output from each of said output ports for detecting phase non-coincidence;
• counting the number of times of detection of phase non-coincidence in each of said output ports;
• and
• deciding the center phase based on the counted number of times of detection of phase non-coincidence.

A circuit for deciding a center phase of data signal input as n-phase serial data, where n is an integer not less than 2, said circuit comprising:

• a serial to parallel converter circuit having a serial data input port for receiving serial data bit stream, and n+1 pieces of output ports for outputting n+1 bits data in parallel obtained on serial to parallel conversion of said serial data at a period equal to n times the period of said data signal;
• a phase comparator circuit comprised of n pieces of comparators, i-th comparator (where i=1 to n) having two input ports for receiving a pair of signals output respectively from i-th and (i+1)-th output ports of said serial to parallel converter circuit to compare phases of the pair of said signals for detecting possible phase non-coincidence therebetween to output a comparison result;
• a counter circuit comprised of n pieces of counters, each receiving the comparison result output from the associated comparator for counting the number of times of phase non-coincidence detected by the associated comparator;
• a maximum value decision circuit having n pieces of input port for receiving n pieces of count values output respectively by said n pieces of counters for detecting the counter which is of the maximum value in the counted number of times of occurrence of phase non-coincidence;
• and
• a selector circuit having n pieces of input ports for receiving data output in parallel from said 1st to n-th output ports of said serial to parallel converter circuit and an input port for receiving the detection result from the maximum value decision circuit to select a signal as the center phase based on the maximum value detection result from among the signals received in parallel at said n pieces of input ports for outputting the selected signal from an output port.