Semiconductor device using complementary clock and signal input state detection circuit used for the same

A signal input state detection circuit for detecting whether a small-amplitude signal is input or not, comprising:

• a first inverter including a first P-channel transistor and a first N-channel transistor inserted in series between a high-voltage terminal and a low-voltage terminal of a power supply, said small-amplitude signal being applied to the gate of said first P-channel transistor and the gate of said first N-channel transistor, said first P-channel transistor having a gate width sufficiently larger than the gate width of said first N-channel transistor;
• a second inverter including a second P-channel transistor and a second N-channel transistor inserted in series between a high-voltage terminal and a low-voltage terminal of a power supply, said small-amplitude signal being applied to the gate of said second P-channel transistor and the gate of said second N-channel transistor, said second N-channel transistor having a gate width sufficiently larger than the gate width of said second P-channel transistor;
• and
• a logic circuit for producing an active signal indicating that said small-amplitude signal is input upon detection that the output of said first inverter assumes a logical value approximate to the potential of said high-voltage terminal and upon detection that the output of said second inverter assumes a logical value approximate to the potential of said low-voltage terminal.

A semiconductor device having a first clock terminal and a second clock terminal, comprising:

• a first clock input circuit connected with the first clock terminal and producing a first internal clock;
• a second clock input circuit connected with the second clock terminal and producing a second internal clock complementary with the first internal clock when an external clock signal is applied to the second clock terminal;
• a ½ phase shift circuit for generating a ½ phase shift signal 180° out of phase with said first internal clock;
• a detection circuit for judging whether said external clock signal is applied to said second clock terminal;
• and
• a switch connected to an output of the second clock input circuit and an output of the ½ phase shift circuit, and selecting one of the second internal clock and the ½ phase shift signal in response to a detection signal from the detection circuit.

A semiconductor device supplied with first and second external clocks, complementary with each other, from an external source, comprising:

• a first clock input circuit supplied with said first external clock for outputting a first internal clock;
• a second clock input circuit supplied with said second external clock for outputting a second internal clock;
• a first 0° phase adjusting circuit for adjusting said first internal clock to be in phase with said first external clock;
• and
• a second 0° phase adjusting circuit for adjusting said second internal clock to be in phase with said second external clock.

A semiconductor device supplied with first and second external clocks complementary with each other from an external source, comprising:

• a first clock input circuit supplied with said first external clock for producing a first internal clock;
• a second clock input circuit supplied with said second external clock for producing a second internal clock;
• a synthesizer for synthesizing the outputs of said first clock input circuit and said second clock input circuit and generating an internal clock of a frequency twice as high as that of said first and second external clocks;
• and
• a 0° phase adjusting circuit for adjusting the internal clock output from said synthesizer to be in phase with selected one of said first external clock and said second external clock.