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US 2002/0153930 A1Published application
Circuit and method for multi-phase alignment
AssigneeBroadcom Corporation
InventorFrank W. Singor
Life of this patent
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Abstract
A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adjusted edges and the unadjusted edges are summed and output as multiple clock signals with a desired pulse edge alignment. The clock signals control switches in a manner to reduce signal dependent sampling distortion.
Claims10
An alignment circuit comprising:
- an input;
- a discriminator coupled to said input, and having a rise output and a fall output;
- a first summer coupled to said rise output and said fall output;
- a rate adjust coupled between said fall output and a second summer;
- an output coupled to said first summer;
- and
- an adjusted output coupled to said second summer.
4 more elements
A method of adjusting pulse edges comprising the steps of:
- (1) receiving a clock signal;
- (2) differentiating between a rising edge and a falling edge in said clock signal;
- (3) coupling said rising edge and said falling edge to a first summer and a second summer;
- (4) adjusting a slope of said falling edge to create an adjusted falling edge;
- (5) summing said adjusted falling edge and said rising edge to output an adjusted clock signal;
- and
- (6) summing said falling edge and said rising edge to output a clock signal.
4 more elements
Dependencies are inferred from the claim text.