Delay locked loop for controlling phase increase or decrease and phase control method thereof

Abstract

A delay locked loop which is capable of adjusting the number of delay devices in a delay line and controlling a phase increase or decrease more precisely than the adjustment by the number of delay devices and a phase control method thereof are provided. The delay locked loop includes a phase detector, a delay line, and a delay time adjuster. The phase detector compares the phase of a reference clock signal with the phase of a feedback clock signal and outputs the phase difference between the reference clock signal and the feedback clock signal as an error control signal. The delay line includes a plurality of first delay devices having a fixed delay time and connected in series. The number of first delay devices connected in series is adjusted in response to a shift signal. The delay line receives an input clock signal and outputs an output clock signal. The delay time adjuster controls a delay time in response to the reference clock signal and the error control signal generated from the phase detector, generates the input clock signal and adjusts the number of first delay devices.

Dependencies are inferred from the claim text.