Generator circuit for voltage ramps and corresponding voltage generation method
AssigneeSTMicroelectronics S.r.l.
InventorsTommaso Zerilli, Maurizio Gaibotti
Life of this patent
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Abstract
A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.
Claims18
A generator circuit for voltage ramps, said generator circuit comprising:
- a first output transistor;
- a differential stage with positive feedback coupled between a first and a second voltage reference, the differential stage including a first output connected to a control terminal of the first output transistor;
- an output terminal coupled to the first output transistor;
- a capacitive charge to be biased with voltage ramps coupled to the first output transistor;
- and
- a second output transistor parallel connected to the first output transistor, the second output transistor having its control terminal connected to a second output of the differential stage.
A method for generating a double ramp voltage signal for a capacitive load, the double ramp voltage signal having a first portion whose slope is higher than a second portion, said method comprising the steps of:
- generating a first phase through a voltage follower stage connected to the capacitive load;
- and
- generating a second phase through a PMOS output stage,
- wherein the phases are alternatively activated depending on the voltage level required by the load.
A memory device including at least one generator circuit for voltage ramps, said generator circuit comprising:
- a first output transistor;
- a differential stage with positive feedback coupled between a first and a second voltage reference, the differential stage including a first output connected to a control terminal of the first output transistor;
- an output terminal coupled to the first output transistor;
- a capacitive charge to be biased with voltage ramps coupled to the first output transistor;
- and
- a second output transistor parallel connected to the first output transistor, the second output transistor having its control terminal connected to a second output of the differential stage.
Dependencies are inferred from the claim text.