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US 2002/0153926 A1Published application
Inverter circuit
AssigneeSeiko Instruments Inc.
InventorHirokazu Yoshizawa
Life of this patent
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Abstract
An inverter circuit is disclosed that prevents flow of a large feedthrough current. The inverter circuit includes depletion type MOS transistor combined with a resistor to impose a current limitation when a feedthrough current flows.
Claims14
An inverter circuit comprising:
- an input terminal;
- an output terminal;
- a first MOS transistor including a first source terminal, a first gate terminal, and a first drain terminal, the first gate terminal being connected to the input terminal, and the first drain terminal being connected to the output terminal;
- a second MOS transistor including a second source terminal, a second gate terminal, and a second drain terminal, the second drain terminal being connected to the first drain terminal and the output terminal, the second source terminal being connected to one end of a resistive element, and the second gate terminal being connected to the other end of the resistive element;
- and
- a third MOS transistor including a third source terminal, a third gate terminal, and a third drain terminal, the third drain terminal being connected to a connection point of the third gate terminal, the second gate terminal, and the other end of the resistive element.
3 more elements
An inverter circuit comprising:
- an input terminal;
- an output terminal;
- a first field-effect transistor including a first source terminal, a first gate terminal, and a first drain terminal, the first gate terminal being connected to the input terminal, and the first drain terminal being connected to the output terminal;
- a second field-effect transistor including a second source terminal, a second gate terminal, and a second drain terminal, the second drain terminal being connected to the first drain terminal and the output terminal, the second source terminal being connected to one end of a resistive element, and the second gate terminal being connected to the other end of the resistive element;
- and
- a third field-effect transistor including a third source terminal, a third gate terminal, and a third drain terminal, the third drain terminal being connected to a connection point of the third gate terminal, the second gate terminal, and the other end of the resistive element.
3 more elements
Dependencies are inferred from the claim text.