Circuit arrangement

A circuit arrangement for controlling a first terminal and a second terminal of a preferably contactless integrated circuit, particularly for testing a CMOS circuit, characterized in that the circuit arrangement (100) comprises:

• at least a control stage (10) which generates, from an external modulation signal (M0) and an external clock signal (C0)
• a first modulation signal (M0);
• a second modulation signal (M2) which is temporally shifted with respect to the first modulation signal (M1);
• a preferably symmetrical first clock signal (C1);
• and
• a preferably symmetrical second clock signal (C2) which is inverted with respect to the first clock signal (C1);
• at least a first driver stage (40),
• which is connected to a first power supply voltage (Udd,1) amplitude-modulated by the first modulation signal (M1) and to a first reference potential (Uss,1) and
• can be impressed with the first clock signal (C1) in such a way that the output voltage (Uo,1) of the first driver stage (40), which can be applied to the first terminal of the integrated circuit, temporally assumes the value of the amplitude-modulated first power supply voltage (Udd,1) and temporally the value of the first reference potential (Uss,1) in accordance with the clock of the first clock signal (C1);
• and
• at least a second driver stage (50),
• which is connected to a second power supply voltage (Udd,2) amplitude-modulated by the second modulation signal (M2) and to a second reference potential (Uss,2) and
• can be impressed with the second clock signal (C2) in such a way that the output voltage (Uo,2) of the second driver stage (50), which can be applied to the second terminal of the integrated circuit, temporally assumes the value of the amplitude-modulated second power supply voltage (Udd,2) and temporally the value of the second reference potential (Uss,2) in accordance with the clock of the second clock signal (C2).