Semiconductor integrated circuit device and IC card
AssigneeHitachi, Ltd.
InventorsKazuki Watanabe, Ryouzou Yoshino, Kenji Nagai, Tatsuya Nishihara
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Abstract
A semiconductor integrated circuit device is provided with an IC chip so as to prevent its circuits from malfunction when the IC chip is cracked. To detect chip cracks, a resistor R01 is disposed at the outer periphery of the area in which one wants to detect the chip crack. If the chip is cracked and the resistance value of the resistor R01 is changed, the resistance change is detected, thereby controlling internal signals such as the power on reset signal and stopping the whole operation of the circuit device so as to prevent the circuits from malfunction. Thus, the system security can also be improved.
Claims35
A semiconductor integrated circuit device provided with a chip on which a transistor and a resistor are formed;
- wherein
- said resistor is provided at least at two sides of the outer periphery of the area which wants to detect the chip crack respectively;
- and
- said resistor is used to detect chip cracks.
A semiconductor integrated circuit device including;
- a current source;
- a resistor connected to said current source serially between first potential and second potential;
- and
- a chip crack detector;
- wherein
- a node between said current source and said resistor is connected to the input terminal of said chip crack detector so that a potential change of said node is detected, thereby a resistance value change of said resistor is detected when a chip crack occurs.
A semiconductor integrated circuit device including;
- first PMOS transistor;
- NMOS transistor connected to said first PMOS transistor serially between first potential and second potential;
- second PMOS transistor;
- an inverter;
- and
- a resistor;
- wherein
- the gate terminal and the drain terminal of said first PMOS transistor are connected to each other;
- a control signal is entered to said gate terminal of said NMOS transistor;
- said second PMOS transistor is connected to said resistor serially between said first potential and said second potential;
- the gate terminal of said second PMOS transistor is connected to the gate terminal of said first PMOS transistor;
- the node between said second PMOS transistor and said resistor is connected to the input terminal of said inverter;
- and
- the output of said inverter and said control signal are entered to a 2-input AND gate.
A semiconductor integrated circuit device including;
- first transistor between first potential and second potential;
- first resistor connected to the source/drain path serially between first potential and second potential;
- second transistor between said first potential and said second potential;
- and
- second resistor connected to the source/drain path of said second transistor between said first potential and said second potential;
- wherein
- the node between said first transistor and said first resistor is connected to the gate of said second transistor;
- the node between said second transistor and said second resistor is connected to the gate of said first transistor;
- and
- a resistance value change of said first or second resistor is detected with the use of an output signal from the node between said first transistor and said first resistor or the node between said second transistor and said second resistor.
A semiconductor integrated circuit device including;
- a logic circuit block;
- a conductor pattern disposed outside said logic circuit block;
- a detector for detecting a resistance change of said conductor pattern;
- and
- a control circuit for controlling whether to stop or inhibit the operation of said logic circuit block based on a result of detection by said detector.
An IC card including;
- a board-like member;
- and
- a semiconductor chip connected to said board-like member directly or indirectly via another member;
- wherein
- said IC card has a built-in detector for detecting cracks of said semiconductor chip.
An IC card including;
- a semiconductor chip provided with a built-in resistor;
- a detector for detecting a resistance value change of said resistor;
- and
- a control circuit for stopping a part or the whole operation of said semiconductor chip in response to the output of said detector.
A semiconductor integrated circuit device including;
- a logic circuit;
- a pattern extended at least in two directions;
- a detector for detecting a resistance value change of said pattern;
- and
- a control circuit for inhibiting or stopping a part or the whole operation of said logic circuit in response to the output from said detector.
A semiconductor integrated circuit device on a chip comprising:
- a first circuit;
- a second circuit;
- and
- a chip crack detection circuit,
- wherein said chip crack detection circuit further includes:
- a first MOS transistor for supplying a current;
- a resistor, the source drain path of said first MOS transistor and said resistor being connected serially between a first potential and a second potential;
- and
- a voltage detector detecting a third potential of a first coupling node between said first MOS transistor and said resistor,
- wherein said voltage detector outputs a high state or a low state according to the third potential, and
- wherein the third potential is changed according to a variation of resistance value of the resistor when said chip is cracked.
Dependencies are inferred from the claim text.