Double planar gated SOI MOSFET structure
AssigneeInternational Business Machines Corporation
InventorsJames W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson, Jed H. Rankin
Life of this patent
Estimating the term…
Abstract
A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.
Claims19
A FET comprising:
- a substrate;
- a source region and a drain region in the substrate, each of said source region and said drain region having a top, bottom and at least two side diffusion surfaces, the source and drain regions separated by a channel region having a top, bottom and side channel surfaces substantially coplanar with corresponding ones of the diffusion surfaces;
- a gate adjacent the top and the side channel surfaces and electrically insulated from the top and side channel surfaces;
- and
- the gate comprising a planar top surface, the planar top surface having a contact for receiving a gate control voltage for controlling the FET.
A method for forming a double gated FET, comprising the steps of:
- forming on a substrate a first and a second line that comprises a channel region;
- etching areas within a silicon layer to form a source and a drain, wherein a side surface of the source and the drain contact opposing end surfaces of the first and second lines;
- and
- forming a gate that contacts a top surface and two side surfaces of the first and second lines and a top surface of the substrate.
The method as recited in step 10, wherein the implants are done in a series at approximately 90 degrees relative to each other.
Dependencies are inferred from the claim text.