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US 2002/0153577 A1Published application
Non-volatile semiconductor memory device and its manufacturing method
AssigneeKabushiki Kaisha Toshiba
InventorsToshitake Yaegashi, Kazuhiro Shimizu, Seiichi Aritome
Life of this patent
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Abstract
In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.
Claims20
A non-volatile semiconductor memory device comprising:
- a plurality of memory cell units each including at least one memory cell formed by stacking a charge storing layer and a control gate layer above a semiconductor substrate in which data is programmed and erased by charging and discharging the charge storing layer;
- a plurality of select transistors each connected to a corresponding one of the memory cell units;
- and
- first and second transistors each for controlling a voltage to be applied to at least one of the memory cells and the select transistor connected thereto, the first transistor having a first gate insulating film, and the second transistor having a second gate insulating film with a different thickness from the first gate insulating film,
- wherein a gate insulating film incorporated in the memory cell, a gate insulating film incorporated in the select transistor and the first gate insulating film are formed of substantially the same film.
2 more elements
A non-volatile semiconductor memory device comprising:
- a plurality of memory cell units each including at least one memory cell formed by stacking a charge storing layer and a control gate layer above a semiconductor substrate in which data is programmed and erased by charging and discharging the charge storing layer;
- a plurality of select transistors each connected to a corresponding one of the memory cell units;
- and
- first and second transistors each for controlling a voltage to be applied to at least one of the memory cells and the select transistor connected thereto, the first transistor having a first gate insulating film, and the second transistor having a second gate insulating film with a different thickness from the first gate insulating film,
- wherein a gate insulating film incorporated in the memory cell and the first gate insulating film are formed substantially the same film, and a gate insulating film incorporated in the select transistor and the second gate insulating film are formed of substantially the same film.
2 more elements
A non-volatile semiconductor memory device comprising:
- a plurality of memory cell units each including at least one memory cell formed by stacking a charge storing layer and a control gate layer above a semiconductor substrate in which data is programmed and erased by charging and discharging the charge storing layer;
- a plurality of select transistors each connected to a corresponding one of the memory cell units;
- and
- first and second transistors each for controlling a voltage to be applied to at least one of the memory cells and the select transistor connected thereto, the first transistor having a first gate insulating film, and the second transistor having a second gate insulating film with a different thickness from the first gate insulating film,
- wherein a gate insulating film incorporated in the select transistor and the second gate insulating film are formed of substantially the same film.
2 more elements
A non-volatile semiconductor memory device comprising:
- a memory cell having a self-aligned double-layer gate structure which includes a gate insulating film, a first conductor serving as a floating gate layer, a second conductor serving as a control gate layer, and an insulating film electrically insulating the first and second conductors, the gate insulating film, the first conductor, the second conductor and the insulating film being formed above a semiconductor substrate;
- and
- a transistor having a gate electrode which is formed above the semiconductor substrate and has a structure wherein a third conductor differing from the second conductor is stacked on the first conductor.
A method of manufacturing a non-volatile semiconductor memory device, comprising the steps of:
- forming, on a first region of a semiconductor substrate, a self-aligned double-layer gate structure which includes a gate insulating film, a first conductor serving as a floating gate layer, a second conductor serving as a control gate layer, and an insulating film electrically insulating the first and second conductors,
- patterning the first conductor into a gate electrode of a transistor above a second region of the semiconductor substrate;
- and
- providing a third conductor on the first conductor patterned in the form of the gate electrode above the second region.
1 more element
A method of manufacturing a non-volatile semiconductor memory device, comprising the steps of:
- sequentially forming, on a semiconductor substrate, a gate insulating film, a first conductor serving as a floating gate layer, an insulating film, and a second conductor serving as a control gate layer;
- patterning the second conductor, the insulating film and the first conductor in a self-aligned manner in a first region of the semiconductor substrate, using a single mask, thereby forming a double-layer gate structure, and removing that portion of the second conductor which is provided on a second region of the semiconductor substrate during the patterning of the second conductor in the first region;
- forming a third conductor on the first conductor in the second region after the patterning of the first conductor in the first region, such that the first and third conductors are electrically connected to each other;
- and
- patterning the third and first conductors into a gate electrode of a transistor in the second region.
2 more elements
Dependencies are inferred from the claim text.