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US 2002/0153545 A1Published application
Semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorShigeki Tomishima
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Abstract
A first level metal interconnection line in a layer below a third level metal interconnection line serving as a main word line MWL is used as a shunting interconnection line and electrically connected to a first level polysilicon interconnection line constituting a sub word line SWL at prescribed intervals. By applying a hierarchical word line structure and a word line shunting structure both, a word line is driven into a selected state at high speed without increasing an array occupancy area and manufacturing steps.
Claims11
A semiconductor memory device comprising:
- a plurality of memory cells arranged in rows and columns;
- a plurality of sub word lines, provided corresponding to the respective memory cell rows, each having memory cells on a corresponding row connected thereto;
- a plurality of main word lines, each provided corresponding to a prescribed number of sub word lines in said plurality of sub word lines and disposed in a first conductive layer, for transmitting a row select signal;
- a plurality of shunting interconnection lines, provided corresponding to the respective sub word lines in a second conductive layer formed under said first conductive layer, each for electrically connecting to a corresponding sub word line at a prescribed interval;
- and
- a plurality of sub word drivers, provided corresponding to the sub word lines, each for driving a corresponding sub word line and a corresponding shunting interconnection line into a selected state according to at least a row select signal on a corresponding main word line.
3 more elements
Dependencies are inferred from the claim text.