Semiconductor integrated circuit device and method of manufacturing the same

A semiconductor integrated circuit device comprising:

• a plurality of memory arrays including a plurality of memory cells formed on a main surface of a semiconductor chip;
• a plurality of fuses formed on the main surface of said semiconductor chip, at least a part of which is arranged between said plurality of memory arrays;
• a plurality of multi-layered first wirings formed in an upper layer of said plurality of memory cells;
• a plurality of internal connection terminals formed of a wiring in the same layer as the uppermost wiring of said plurality of first wirings;
• a passivation layer formed so as to cover said plurality of first wirings and said plurality of fuses and selectively exposing said plurality of internal connection terminals;
• a plurality of second wirings formed over said passivation layer, each having one end electrically connected to said internal connection terminal;
• an uppermost protection layer formed so as to cover said plurality of second wirings and selectively exposing the other ends of said plurality of second wirings;
• and
• a plurality of external connection terminals formed on the other ends of said plurality of second wirings,
• wherein at least a part of said plurality of second wirings are arranged over at least a part of said plurality of fuses.

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) forming a plurality of memory cells in a plurality of chip areas on a main surface of a semiconductor wafer, forming a plurality of multi-layered first wirings in an upper layer of said plurality of memory cells, and forming a plurality of fuses in said plurality of chip areas during the step of forming said plurality of memory cells or the step of forming said plurality of first wirings;
• (b) forming a passivation layer over said plurality of first wirings and said plurality of fuses, and removing parts of said passivation layers to expose a wiring in the same layer as the uppermost wiring of said plurality of first wirings, thereby forming a plurality of internal connection terminals;
• (c) removing other parts of said passivation layers, thereby forming fuse openings over each of said plurality of fuses;
• (d) after said step (b), conducting a probe test to detect presence of defect cells, and irradiating laser to said fuse through a predetermined fuse opening of said plurality of fuse openings, thereby cutting said fuse by fusion when said probe test detects defect cells;
• (e) after said step (d), forming an elastomer layer on said passivation layer, said passivation layer being formed also in said plurality of fuse openings;
• (f) performing a heat treatment to said elastomer layer, thereby curing said elastomer layer;
• (g) forming a plurality of second wirings having one ends electrically connected to said internal connection terminals over said elastomer layer, then forming an uppermost protection layer on said plurality of second wirings and removing a part of said uppermost protection layer, thereby selectively exposing the other ends of said plurality of second wirings;
• (h) performing a heat treatment to said uppermost protection layer, thereby curing said uppermost protection layer;
• and
• (i) forming a plurality of external connection terminals at the other ends of said plurality of second wirings, then cutting said semiconductor wafer into said chip areas, thereby obtaining a plurality of semiconductor chips,
• wherein a temperature of each of the heat treatments in said steps (f) and (h) is set at a certain temperature so as not to change predetermined characteristics of said plurality of memory cells.

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) forming a plurality of memory cells in a plurality of chip areas on a main surface of a semiconductor wafer, forming a plurality of multi-layered first wirings in an upper layer of said plurality of memory cells, and forming a plurality of fuses in said plurality of chip areas during the step of forming said plurality of memory cells or the step of forming said plurality of first wirings;
• (b) forming a passivation layer over said plurality of first wirings and said plurality of fuses, and removing parts of said passivation layers to expose a wiring in the same layer as the uppermost wiring of said plurality of first wirings, thereby forming a plurality of internal connection terminals;
• (c) removing other parts of said passivation layers, thereby forming fuse openings over each of said plurality of fuses;
• (d) after said step (b), conducting a probe test to detect presence of defect cells, and irradiating laser to said fuse through a predetermined fuse opening of said plurality of fuse openings, thereby cutting said fuse by fusion when said probe test detects defect cells;
• (e) forming a plurality of second wirings having one ends electrically connected to said internal connection terminals over said passivation layer, then forming an uppermost protection layer on said plurality of second wirings and removing a part of said uppermost protection layer, thereby selectively exposing the other ends of said plurality of second wirings;
• (f) performing a heat treatment to said uppermost protection layer, thereby curing said uppermost protection layer;
• and
• (g) forming a plurality of external connection terminals at the other ends of said plurality of second wirings, then cutting said semiconductor wafer into said chip areas, thereby obtaining a plurality of semiconductor chips,
• wherein a temperature of the heat treatment in said step (f) is set at a certain temperature so as not to change predetermined characteristics of said plurality of memory cells.