Semiconductor device and method for fabricating the same
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorMizuki Segawa
Life of this patent
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Abstract
A gate insulating film, a gate electrode, a gate-top protection film, LDD layers and nitride film sidewalls are formed on a semiconductor substrate. Source/drain regions are formed in the semiconductor substrate. After deposition of an interlayer insulating film on the resultant substrate, a hole is formed through the interlayer insulating film and the gate-top protection film to reach the gate electrode, and a gate contact is formed by filling the hole. The gate-top protection film has an opening exposing part of a portion of the area on the top surface of the gate electrode other than the region in contact with the gate contact. This facilitates external diffusion of hydrogen during annealing, or recovery from a fixed level and a damage layer during sintering.
Claims16
A semiconductor device comprising:
- a semiconductor substrate;
- a gate insulating film formed on the semiconductor substrate;
- a gate electrode made of a conductive material formed on the gate insulating film;
- a gate-top protection film made of an insulating material formed on the gate electrode;
- source/drain regions formed by implanting impurities in regions of the semiconductor substrate located on both sides of the gate electrode;
- an interlayer insulating film formed on the resultant substrate;
- and
- a gate contact member formed by filling a gate contact hole with a conductive material, the gate contact hole extending through the interlayer insulating film and the gate-top protection film to reach the gate electrode,
- wherein the gate-top protection film has an opening exposing part of a portion of an area located on the top surface of the gate electrode other than the region of the gate contact hole.
A method for fabricating a semiconductor device, comprising the steps of:
- (a) forming a gate insulating film on a semiconductor substrate;
- (b) depositing a conductive film on the gate insulating film;
- (c) forming a silicon nitride film covering both surfaces of the semiconductor substrate after the step (b);
- (d) patterning the conductive film and a portion of the silicon nitride film located on the principal plane side of the semiconductor substrate to form a gate electrode and a gate-top protection film;
- (e) implanting impurity ions in the semiconductor substrate to form source/drain regions after the step (d);
- (f) performing annealing for activation of the impurities implanted in the source/drain regions;
- and
- (g) removing a portion of the silicon nitride film located on the back side of the semiconductor substrate after the step (c) and before the step (f).
A method for fabricating a semiconductor device, comprising the steps of:
- (a) forming a gate insulating film on a semiconductor substrate;
- (b) depositing a conductive film on the gate insulating film;
- (c) forming a silicon nitride film covering the principal plane of the semiconductor substrate after the step (b);
- (d) patterning the silicon nitride film to form a gate-top protection film only on part of an area located immediately above a gate electrode of the conductive film;
- (e) patterning the conductive film to form the gate electrode;
- (f) implanting impurity ions in the semiconductor substrate to form source/drain regions after the step (e);
- (g) performing annealing for activation of the impurities implanted in the source/drain regions;
- (h) forming an interlayer insulating film on the resultant substrate;
- and
- (i) forming contact holes through the interlayer insulating film to reach the source/drain regions, the contact holes overlapping the gate electrode only via the gate-top protection film at any overlap portion with the gate electrode.
A method for fabricating a semiconductor device, comprising the steps of:
- (a) forming a gate insulating film on a semiconductor substrate;
- (b) depositing a conductive film on the gate insulating film;
- (c) forming a silicon nitride film covering the principal plane of the semiconductor substrate after the step (b);
- (d) patterning the silicon nitride film and the conductive film to form a gate-top protection film and a gate electrode;
- (e) implanting impurity ions in the semiconductor substrate to form source/drain regions after the step (d);
- (f) forming an interlayer insulating film on the resultant substrate after the step (e);
- (g) forming a contact hole through the interlayer insulating film and the gate-top protection film to reach the gate electrode;
- and
- (h) performing heat treatment for activation of the impurities implanted in the source/drain regions after the step (g).
Dependencies are inferred from the claim text.