Low power CSD linear phase FIR filter architecture using virtual common subexpression and filter design method therefor

A method for receiving and filtering input signals of digital samples of k bits (k:

• natural numbers more than 4) in a digital filter having filter characteristics that are created by filter coefficients being expressed as CSD code words of n bits (n:
• natural numbers more than 2), comprising the steps:
• creating as a virtual common subexpression common subexpressions created by bit-shift, bit-add, or bit-inversion of random coefficient subexpressions out of the digital filter coefficients, thereafter shifting the digital samples by the number of bits corresponding to the common subexpression and the virtual common subexpression;
• adding up all the digital samples shifted by the number of bits corresponding to the common subexpressions to obtain a composite output value of a common coefficient tap line;
• obtaining composite output values of random coefficient tap lines by adding up the digital samples shifted by the number of bits corresponding to the virtual common subexpression and the composite output value of the common coefficient tap line being used as a common input;
• and
• performing in order delaying and adding to create filter output values by subsequent compositions of the composite output values of the common coefficient tap lines and the composite output values of the random coefficient tap lines.

A digital filter, comprising:

• a shift register group including first shift register members each receiving digital samples of k bits as input signals and shifting the received digital samples by bit shift values of filter coefficients that are defined as common subexpressions out of filter coefficients that are expressed as code words of n bits within CSD code, and second shift register members shifting code words of the other filter coefficients that are not defined as the common subexpressions by using the code words of the common subexpressions;
• a adder group including first composite members adding up the shifted digital samples that are output from the first shift register members to provide them to common tap lines, and second composite members for adding the shifted digital samples that are output from the second shift register members to the composite outputs of the common tap lines to provide the results to each of corresponding tap lines;
• a delay group including a plurality of delayers connected to the tap lines and being connected in series from one another to provide delay to the composite outputs;
• and
• an output adder group including a plurality of adders for adding up the outputs of the delayers and the composite outputs of the tap lines to create digital output signals of k bit(s).

An N tap CSD digital filter having filter coefficients that are expressed as CSD codes, comprising:

• a shift register group including first shift register members receiving digital samples of a plurality of bits as input signals and shifting the received digital samples by bit shift values of filter coefficients that are defined as common subexpressions out of the filter coefficients, and second shift register members shifting code words of the other filter coefficients that are not defined as the common subexpressions by using the code words of the common subexpressions;
• an adder group including first composite members adding up the shifted digital samples that are output from the first shift register members to provide them to common tap lines, and second composite members for adding the shifted digital samples that are output from the second shift register members to the composite outputs of the common tap lines to provide the results to each of the corresponding tap lines;
• a delay group including a plurality of delayers connected to the tap lines and being connected in series from one another to provide delay to the composite outputs;
• and
• an output adder group including a plurality of adders for adding up the outputs of the delayers and the composite outputs of the tap lines to create digital output signals of k bit(s).

A digital filter comprising:

• at least one shift register for receiving digital samples of input signals and shifting the received digital samples by bit-shift values of filter coefficients that are defined relative to a virtual common subexpression;
• a first adder for adding shifted digital samples that are output from the at least one shift register to drive a common tap line;
• a second adder for adding shifted digital samples that are output from the at least one shift register to the output of the common tap line to drive a tap line corresponding to a filter coefficient;
• and
• at least one delay unit connected to a tap line for delaying an output signal component.

A digital filter comprising:

• means for receiving digital samples of input signals;
• means for shifting the received digital samples by bit-shift values of filter coefficients that are defined relative to a virtual common subexpression;
• means for adding shifted digital samples to drive a common tap line;
• means for adding shifted digital samples to the output of the common tap line to drive a tap line corresponding to a filter coefficient;
• and
• means for delaying an output signal component corresponding to a tap line.

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for digitally filtering input signals, the method steps comprising:

• receiving digital samples of the input signals;
• shifting the received digital samples by bit-shift values of filter coefficients that are defined relative to a virtual common subexpression;
• adding shifted digital samples to drive a common tap line;
• adding shifted digital samples to the output of the common tap line to drive a tap line corresponding to a filter coefficient;
• and
• delaying an output signal component corresponding to at least one of a filter coefficient and a tap line.