Silicon wafers for CMOS and other integrated circuits

A method of manufacturing a semiconductor wafer, the method comprising:

• growing a silicon ingot substantially uniformly doped with boron, wherein the ingot has a resistivity in a range of about 10 to 1,000 milli-ohm-centimeter;
• slicing the ingot into individual wafers;
• polishing a surface of at least one of the wafers;
• heat treating the at least one wafer in an atmosphere containing hydrogen at a temperature of at least about 1,000° C. to achieve a resistivity in a region near the polished surface of the wafer in a range of about 0.5 to 10 ohm-centimeter.

A silicon semiconductor wafer comprising:

• a polished surface;
• a substantially uniformly boron-doped bulk region having a resistivity in a range of about 10 to 1,000 milli-ohm-centimeter;
• and
• a reduced boron concentration layer near the polished surface, wherein the reduced boron concentration layer extends along substantially the entire polished surface and has a boron gradient that increases with increasing depth from the polished surface to a depth in a range of about 0.1 to 1.0, wherein the reduced boron concentration layer has a resistivity in a range of about 0.5 to 10 ohm-centimeter.