Computer readable storage medium

A computer program stored on a storage medium for performing wiring condition processing for a semiconductor integrated circuit, said computer program when executed causes a computer to perform the steps of:

• creating layout information to determine a layout of devices on the semiconductor integrated circuit based on logic information describing connections of the devices on the semiconductor integrated circuit;
• determining a virtual wiring path from the layout information;
• calculating a wiring delay value based on the virtual wiring path;
• upon the calculated wiring delay value of the virtual wiring path exceeding a predetermined reference value, calculating a wiring delay value of the virtual wiring path when a wiring layer with a small wiring load capacity is used at a predetermined usage ratio;
• upon the wiring delay value of the virtual wiring path when the wiring layer with a small wiring load capacity is used at the predetermined usage ratio not exceeding the predetermined reference value, calculating a minimum usage ratio of the wide wiring line such that the wiring delay value satisfies the predetermined reference value;
• and
• adding information on the calculated minimum usage ratio of the wiring layer with a small wiring load capacity to information on the virtual wiring path to create wiring condition information.

A computer program stored on a storage medium for performing wiring condition processing for a semiconductor integrated circuit, said computer program when executed causes a computer to perform the steps of:

• creating layout information to determine a layout of devices on the semiconductor integrated circuit based on logic information describing connections of the devices on the semiconductor integrated circuit;
• determining a virtual wiring path from the layout information;
• calculating a wiring delay value based on the virtual wiring path;
• upon the calculated wiring delay value of the virtual wiring path exceeding a predetermined reference value, calculating a wiring delay value of the virtual wiring path when parallel wiring lines are used at a predetermined usage ratio;
• upon the wiring delay value of the virtual wiring path when the parallel wiring lines are used at the predetermined usage ratio not exceeding the predetermined reference value, calculating a minimum usage ratio of the wide wiring line such that the wiring delay value satisfies the predetermined reference value;
• and
• adding information on the calculated minimum usage ratio of the wiring layer with parallel wiring lines to information on the virtual wiring path to create wiring condition information.

A computer program stored on a storage medium for performing wiring condition processing for a semiconductor integrated circuit, said computer program when executed causes a computer to perform the steps of:

• creating layout information to determine a layout of devices on the semiconductor integrated circuit based on logic information describing connections of the devices on the semiconductor integrated circuit;
• determining a virtual wiring path from the layout information;
• calculating a wiring delay value based on the virtual wiring path;
• upon the calculated wiring delay value of the virtual wiring path exceeding a predetermined reference value, calculating a wiring delay value of the virtual wiring path when a wide wiring line is used at a predetermined usage ratio of the wiring line and parallel wiring lines are used at a usage ratio which is less than another predetermined usage ratio;
• upon the wiring delay value of the virtual wiring path when the wide wiring line is used at the predetermined usage ratio of the wiring line and the parallel wiring lines are used at a usage ratio which is less than another predetermined usage ratio not exceeding the predetermined reference value, calculating a ratio of a length of the wiring line along which parallel wiring lines should not run to satisfy the reference value;
• and
• adding information on the calculated usage ratio of the wiring layer to information on the virtual wiring path to create wiring condition information.