State management in a co-verification system
OwnerMichael C. Brouhard, John Wilsoninventors
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Abstract
A method and apparatus for state management in a co-verification system is described. The invention allows acceleration of co-simulation without loss of information that can occur from independent simulation of software and hardware components of a design. For example, counters included in a hardware component that are influenced by software components are simulated and updated by the software simulator when simulation of hardware and software is not synchronized. When the counter or other hardware component that is maintained by software simulation causes a hardware event (e.g., an interrupt) to occur, co-simulation is resynchronized and the hardware component is updated. Improved acceleration of co-simulation is thereby provided.
Claims18
A method of co-verification of a design having a first portion and a second portion, the method comprising:
- detecting a transition from a synchronized co-verification mode to an accelerated co-verification mode;
- verifying the first portion and the second portion independently in response to the transition;
- maintaining an architectural state corresponding to the second portion based on verification of the first portion, wherein the architectural state is maintained by as part of verification of the first portion;
- and
- transitioning to synchronized co-verification mode in response to a predetermined architectural state.
A machine-readable medium having stored thereon sequences of instruction to perform co-verification of a design having a first portion and a second portion, the sequences of instructions, when executed by one or more processors cause the one or more processors to:
- detect a transition from a synchronized co-verification mode to an accelerated co-verification mode;
- verify the first portion and the second portion independently in response to the transition;
- maintain at least some of an architectural state corresponding to the second portion based on verification of the first portion, wherein the architectural state is maintained by components to verify the first portion;
- and
- transition to synchronized co-verification mode in response to a predetermined architectural state.
An apparatus for co-verification of a design having a first portion and a second portion, the apparatus comprising:
- means for detecting a transition from a synchronized co-verification mode to an accelerated co-verification mode;
- means for verifying the first portion and the second portion independently in response to the transition;
- means for maintaining at least some of an architectural state corresponding to the second portion based on verification of the first portion, wherein the architectural state is maintained by components to verify the first portion;
- and
- means for transitioning to synchronized co-verification mode in response to a predetermined architectural state.
Dependencies are inferred from the claim text.