Process and system for management of test access port (TAP) functions
AssigneeSTMicroelectronics S.r.I.
InventorAmedeo La Scala
Life of this patent
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Abstract
Management of Test Access Port functions of a plurality of components arranged on a single chip by selectively driving the TAP function of each of the components with respective clocks, whilst the further signals for driving the TAP function are used in a shared mode among the various components. Preferably, associated with the aforesaid clocks is a pull-down function for selectively blanking the respective clocks in conditions of non-use. In a preferred way, the aforesaid dedicated clocks are generated on board the chip.
Claims17
A process for management of a Test Access Port function in a plurality of components arranged on a single chip, each of said components provided with a respective TAP function adapted to be driven by a respective clock and by at least one further signal, comprising the operations of:
- using said at least one further signal in a shared way between the TAP functions of the plurality of components;
- and
- selectively driving the TAP functions of the plurality of components with respective clocks.
A system for management of a Test Access Port function in a plurality of components arranged on a single chip, each of the components provided with a respective TAP function adapted to be driven by a respective clock, comprising:
- at least one line for use of at least one further signal in a shared way between the TAP functions of the plurality of components;
- and
- at least one generator of a respective clock for selectively driving the TAP functions of the plurality of components.
A method of managing a Test Access Port (TAP) function in conjunction with a plurality of components on a single chip, comprising:
- providing each component of the plurality of components with a respective TAP function;
- providing each component of the plurality of components with a respective clock signal;
- providing at least one shared line for use by at least one further signal among the TAP functions of the plurality of components;
- and
- selectively driving the respective TAP functions of the plurality of components with the respective clock signals.
A system for managing testing of a plurality of components arranged on a single chip, the system comprising:
- a Test Access Port function associated with each component of the plurality of components;
- a plurality of clock generators, each clock generator associated with a respective TAP function for selectively driving the TAP function with a respective clock signal;
- and
- at least one shared line coupled to each component of the plurality of components and configured to carry at least one further signal.
Dependencies are inferred from the claim text.