Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

An apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test mode, where N>1 and each domain has a plurality of scan cells, said apparatus comprising:

• (a) means for generating and loading N pseudorandom stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during the shift operation;
• (b) means for applying an ordered sequence of capture clocks to all said scan cells within said N clock domains during the capture operation;
• (c) means for compacting N output responses of all said scan cells to signatures during the compact operation;
• and
• (d) means for repeating the steps of (a)-(c) until a predetermined limiting criteria is reached, wherein (a) and (c) occur substantially concurrently.

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test mode, where N>1 and each domain has a plurality of scan cells, said method comprising the steps of:

• (a) shifting in N pseudorandom stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during the shift-in operation;
• (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains during the capture operation;
• and
• (c) shifting out N output responses of all said scan cells for analysis during the shift-out operation.

A computer-aided design (CAD) system for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test mode, where N>1 and each domain has a plurality of scan cells, said CAD system comprising the computer-implemented steps of:

• (a) compiling the HDL code or netlist that represents said integrated circuit or circuit assembly in physical form into a design database;
• (b) performing self-test rule check for checking whether said design database contains any multiple-capture self-test rule violations;
• (c) performing self-test rule repair until all said multiple-capture self-test rule violations have been fixed;
• (d) performing multiple-capture self-test synthesis for generating a self-test HDL code or netlist;
• and
• (e) generating HDL test benches and ATE test programs for verifying the correctness of said self-test HDL code or netlist.

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test mode, where N>1 and each domain has a plurality of scan cells, said method comprising the steps of:

• (a) generating and loading N predetermined stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during the shift operation;
• (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains where one or more capture clocks must contain two or more clock pulses during the capture operation;
• (c) comparing N output responses directly with their expected output responses for all said scan cells within said N clock domains and indicating errors immediately during the compare operation;
• and
• (d) repeating the steps of (a)-(c) until a predetermined limiting criteria is reached, wherein (a) and (c) occur substantially concurrently.

An apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test mode, where N>1 and each domain has a plurality of scan cells, said apparatus comprising:

• (a) means for generating and loading N predetermined stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during the shift operation;
• (b) means for applying an ordered sequence of capture clocks to all said scan cells within said N clock domains where one or more capture clocks must contain two or more clock pulses during the capture operation;
• (c) means for comparing N output responses directly with their expected output responses for all said scan cells within said N clock domains and indicating errors immediately during the compare operation;
• and
• (d) means for repeating the steps of (a)-(c) until a predetermined limiting criteria is reached, wherein (a) and (c) occur substantially concurrently.

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test mode, where N>1 and each domain has a plurality of scan cells, said method comprising the steps of:

• (a) shifting in N predetermined stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during the shift-in operation;
• (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains where one or more capture clocks must contain two or more clock pulses during the capture operation;
• and
• (c) shifting out N output responses of all said scan cells for analysis during the shift-out operation.

A computer-aided design (CAD) system for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test mode, where N>1 and each domain has a plurality of scan cells, said CAD system comprising the computer-implemented steps of:

• (a) compiling the HDL code or netlist that represents said integrated circuit or circuit assembly in physical form into a design database;
• (b) performing scan rule check for checking whether said design database contains any multiple-capture scan rule violations;
• (c) performing scan rule repair until all said multiple-capture scan rule violations have been fixed;
• (d) performing multiple-capture scan synthesis for generating a scan HDL netlist;
• and
• (e) generating HDL test benches and ATE test programs, where one or more capture clocks must contain two or more clock pulses, for verifying the correctness of said scan HDL netlist.