Integrated circuit device having boundary scan register
AssigneeFujitsu Limited
InventorMasahito Suzuki
Life of this patent
Estimating the term…
Abstract
An integrated circuit device having a plurality of input terminals comprises: a plurality of input buffers provided in correspondence to the plurality of input terminals; a pluralityof serialparallelconversioncircuitsforconverting, inserial-parallel, outputs of the inputbuffers, respectively; and a plurality of boundary scan registers which are provided in correspondence to each input terminal. The output of the input buffer is supplied to the serial parallel conversion circuit and the boundary scan register in parallel, to restrict a delay element between the input buffer and the serial parallel conversion circuit at a minimum.
Claims10
An integrated circuit device having a plurality of input terminals, comprising:
- a plurality of input buffers provided to the plurality of input terminals;
- a plurality of serial parallel conversion circuits for converting, in serial-parallel, outputs of the input buffers, respectively;
- and
- a plurality of boundary scan registers which input selectively an output of the input buffer or an input of a test data, holds the input data, and outputs selectively the held input data or an output of the serial parallel conversion circuit,
- wherein the plurality of boundary scan registers are connected serially to constitute a shift register.
An integrated circuit device having a plurality of output terminals, comprising:
- a plurality of parallel serial conversion circuits for converting, in parallel-serial, an internal signal;
- a plurality of output buffers which are provided to the plurality of output terminals, and to which an output of the parallel serial conversion circuit is supplied;
- and
- a plurality of boundary scan registers which selectively input the internal signal or an input of a test data, hold the input data, and selectively output the held input data or an output of the output buffer,
- wherein the plurality of boundary scan registers are serially connected to constitute a shift register.
An integrated circuit device having a plurality of output terminals, comprising:
- a plurality of parallel serial conversion circuits for converting, in parallel-serial, an internal signal;
- a plurality of output buffers which are provided to the plurality of output terminals, and to which an output of the parallel serial conversion circuit is supplied;
- a plurality of boundary scan registers which selectively input the internal signal or an input of the test data, hold the input data, and selectively output the held input data or an output of the parallel serial conversion circuit,
- wherein the plurality of boundary scan registers are serially connected to constitute a shift register.
Dependencies are inferred from the claim text.