Dynamic processor configuration and power-up

A system, comprising:

• a processor having programmable fuse block programmed with at least one configuration signal;
• logic coupled to the processor to read the configuration signal and in response to generate a value specified by the configuration signal;
• a control signal coupled to the processor and the logic to prevent the logic from reading the configuration signal until a predetermined event occurs.

A processor, comprising:

• front-end logic to receive a control signal;
• and
• configuration signal logic coupled to the front-end logic to inhibit booting up of the processor in response to the front-end logic receiving the control signal.

An apparatus, comprising:

• a machine-readable medium having stored thereon instructions for causing a processor to:
• apply a control signal to a processor from a voltage regulator to inhibit a platform normal boot process until at least one configuration signal can be read from a programmable fuse block in the processor.