Calibrating return time
AssigneeIntel Corporation
InventorsThomas D. Simon, Rajeevan Amirtharajah
Life of this patent
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Abstract
Calibrating return time includes determining clock calibration information based on clock signals local to a master device and return clock signals corresponding to each of at least two slave devices, storing clock calibration information with respect to each of the slave devices with which the master device will communicate using a bus, and, after the clock calibration information has been stored, resynchronizing data signals that are received from each of the slave devices based on the corresponding stored clock calibration information.
Claims30
A method comprising:
- determining clock calibration information based on clock signals local to a master device and return clock signals corresponding to each of at least two slave devices;
- storing clock calibration information with respect to each of the slave devices with which the master device will communicate using a bus;
- and
- after the clock calibration information has been stored, resynchronizing data signals that are received from each of the slave devices based on the corresponding stored clock calibration information.
An apparatus comprising
- input ports to receive respectively a first clock signal and a second clock signal to be resynchronized to the first clock signal;
- two arbiter circuits and two delay circuits, one of the arbiter circuits to receive the first clock signal and a delayed version of the second clock signal, the other arbiter circuit to receive the second clock signal and a delayed version of the first clock signal, and both arbiter circuits to determine an ordering of the two signals which it is connected to receive;
- and
- output ports to send the outputs of the arbiter circuits to a storage device.
An apparatus comprising:
- means for receiving respectively a first clock signal and a second clock signal to be resynchronized to the first clock signal;
- means for receiving the first clock signal and a delayed version of the second clock signal;
- means for receiving the second clock signal and a delayed version of the first clock signal;
- and
- output ports to send the outputs of the means for receiving to a storage device.
An apparatus comprising:
- a port to receive data signals to be resynchronized;
- a multiplexor to either pass each data signal or pass a delayed version of each data signal;
- a control port that receives a value for each data signal that determines whether the multiplexor passes the data signal or passes a delayed version of the data signal;
- and
- a port to send the passed data signals and passed delayed data signals to circuitry.
An apparatus comprising:
- means for receiving data signals to be resynchronized;
- means for either passing each data signal or passing a delayed version of each data signal;
- and
- means for sending the passed data signals and passed delayed data signals to circuitry.
Dependencies are inferred from the claim text.