Stall control
AssigneeSiroyan Limited
InventorsKar-Lik Kasim Wong, Nigel Peter Topham
Life of this patent
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Abstract
Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages (142, 146) for executing an instruction on successive clock cycles. The processors include distributed stall control circuitry (148, 150, 152, 154) which allow an instruction in one pipeline to become temporarily out of step with an instruction in another pipeline. This may allow time for a global signal, such as a global stall signal, to be distributed.
Claims22
A processor comprising:
- a plurality of pipelines, each pipeline having a plurality of pipeline stages for executing an instruction on successive clock cycles;
- and
- stall control circuitry which controls the stalling of instructions in the pipelines in response to a stall signal generated in any one of the pipelines;
- wherein the stall control circuitry is adapted to stall the execution of an instruction in a pipeline not generating the stall signal at least one clock cycle later than the execution of an instruction in a pipeline generating the stall signal, and to release the stall in the pipeline not generating the stall signal at least one clock cycle later than the stall in the pipeline generating the stall signal.
A processor comprising a plurality of pipelines, each pipeline having a plurality of pipeline stages which carry out a series of operations on information passing through the pipelines, two or more pipeline stages each being provided with associated stall control circuitry which control the stalling of that pipeline stage, the control circuitry comprising:
- a circuit portion which generates a hold signal for stalling the associated pipeline stage in response to either a local stall signal generated by that pipeline stage or a global stall signal generated by another pipeline;
- a circuit portion which generates a global stall signal for stalling another pipeline in response to said local stall signal;
- and
- a circuit portion which delays the global stall signal such that the global stall signal is asserted a given number of clock cycles later than the hold signal is asserted, and the global stall signal is released the same number of clock cycles later than the hold signal is released.
A processor comprising a plurality of pipelines, each pipeline having a plurality of pipeline stages for carrying out a series of operations on information passing through the pipelines, two or more pipeline stages each being provided with associated stall control circuitry for controlling the stalling of that pipeline stage, the control circuitry comprising:
- means for generating a hold signal for stalling the associated pipeline stage in response to either a local stall signal generated by that pipeline stage or a global stall signal generated by another pipeline;
- means for generating a global stall signal for stalling another pipeline in response to said local stall signal;
- and
- means for delaying the global stall signal such that the global stall signal is asserted a given number of clock cycles later than the hold signal is asserted, and the global stall signal is released the same number of clock cycles later than the hold signal is released.
A processor comprising:
- a plurality of pipelines, each pipeline having a plurality of pipeline stages for executing an instruction on successive clock cycles;
- and
- stalling means for stalling the execution of instructions in all of the pipelines in response to a stall signal generated in any one of the pipelines;
- wherein the stalling means is adapted to stall the execution of an instruction in a pipeline not generating the stall signal at least one clock cycle later than the execution of an instruction in a pipeline generating the stall signal, and to release the stall in the pipeline not generating the stall signal at least one clock cycle later than the stall in the pipeline generating the stall signal.
A method of operating a processor, the processor comprising a plurality of pipelines, each pipeline having a plurality of pipeline stages for executing instructions on successive clock cycles, each pipeline being capable of generating a stall signal, the method comprising:
- generating a stall signal in one of the pipelines;
- stalling the execution of an instruction in the pipeline generating the stall signal;
- stalling the execution of an instruction in a pipeline not generating the stall signal at least one clock cycle later;
- releasing the stall in the pipeline generating the stall signal;
- and
- releasing the stall in the pipeline not generating the stall signal at least one clock cycle later.
Dependencies are inferred from the claim text.