Data processer and data processing system

A data processor, comprising:

• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• and
• a bus controller which controls access to an external bus in response to the direction by said instruction execution unit,
• said bus controller having a plurality of instruction buffers each holding bits of an instruction fetched by said instruction execution unit, a flag for each of instruction buffers, and a buffer controller circuit;
• said buffer controller circuit being served for allocating to each of said instruction buffers one of specific values that plural lower bits of an instruction address may take;
• prefetching, when an instruction is fetched which has a start address indicated by said plural lower bits, instructions to the instruction buffers corresponding to the address order in the range from the address that follows to the starting instruction address of fetched instruction designated to by said plural lower bits to the final address of instructions indicated by said plural lower bits;
• prefetching, when an instruction fetch is performed by a branch instruction for an instruction at the branch destination address, instruction to the instruction buffers corresponding to the address order to the addresses in the range from the address following the address of the fetched instruction to the final address indicated by said plural lower bits;
• setting the appropriate flag to valid in response to the instruction prefetch;
• outputting to said instruction execution unit the instruction in the instruction buffer under the condition that the flag of the corresponding instruction buffer allocated in correspondence with the value of said plural lower bits of the instruction address of the instruction to be fetched by said instruction execution unit is set to valid.

A data processing system, comprising:

• a data processor, formed on a single semiconductor chip, including:
• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• and
• a bus controller having a plurality of instruction buffers, a flag for each of instruction buffers, and a buffer controller circuit, for controlling access to an external bus in response to a command from said instruction execution unit;
• and
• a memory for storing operation programs for said data processor, said memory being a target of external bus access by said bus controller;
• said buffer controller circuit being served for allocating to each of said instruction buffers one of specific values that plural lower bits of an instruction address may take;
• prefetching, when an instruction is fetched which has a start address indicated by said plural lower bits, instructions to the instruction buffers corresponding to the address order in the range from the address that follows to the starting instruction address of fetched instruction designated to by said plural lower bits to the final address of instructions indicated by said plural lower bits;
• prefetching, when an instruction fetch is performed by a branch instruction for an instruction at the branch destination address, instruction to the instruction buffers corresponding to the address order to the addresses in the range from the address following the address of the fetched instruction to the final address indicated by said plural lower bits;
• setting the appropriate flag to valid in response to the instruction prefetch;
• outputting to said instruction execution unit the instruction in the instruction buffer under the condition that the flag of the corresponding instruction buffer allocated in correspondence with the value of said plural lower bits of the instruction address of the instruction to be fetched by said instruction execution unit is set to valid.

A data processing system, comprising:

• a data processor, formed on a single semiconductor chip, including:
• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• and
• a bus controller having a plurality of instruction buffers each holding bits of instructions to be fetched by said instruction execution unit, a flag for each of instruction buffers, and a buffer controller circuit, for controlling access to an external bus in response to a command from said instruction execution unit;
• and
• a memory for storing operation programs for said data processor, said memory being a target of external bus access by said bus controller;
• said buffer controller circuit being served for allocating to each of said instruction buffers one of specific values that plural lower bits of an instruction address may take;
• prefetching, when an instruction is fetched which has a start address indicated by said plural lower bits, instructions to the instruction buffers corresponding to the address order in the range from the address that follows to the starting instruction address of fetched instruction designated to by said plural lower bits to the final address of instructions indicated by said plural lower bits;
• prefetching, when an instruction fetch is performed by a branch instruction for an instruction at the branch destination address, instruction to the instruction buffers corresponding to the address order to the addresses in the range from the address following the address of the fetched instruction to the final address indicated by said plural lower bits;
• setting the appropriate flag to valid in response to the instruction prefetch;
• outputting to said instruction execution unit the instruction in the instruction buffer under the condition that the flag of the corresponding instruction buffer allocated in correspondence with the value of said plural lower bits of the instruction address of the instruction to be fetched by said instruction execution unit is set to valid, setting to invalid the appropriate flag corresponding to the instruction prefetched into an instruction buffer in response to the output thereof, enabling the instruction to be prefetched to corresponding instruction buffers under the condition that said flag is set to invalid, and initializes all of said flags to invalid in response to an instruction fetch command according to a branch instruction.

A cellular phone, comprising:

• a data processor, a memory, a bus connected to said data processor and to said memory;
• said memory storing at least programs for protocol handling or system control process;
• said data processor including:
• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• and
• a bus controller which controls access to a memory in response to a signal from said instruction execution unit, said bus controller having a plurality of instruction buffers, a flag for each of instruction buffers, and a buffer controller circuit;
• said buffer controller circuit being served for allocating to each of said instruction buffers one of specific values that plural lower bits of an instruction address may take;
• when an instruction fetch is executed from an instruction address corresponding to the minimal value expressed by the plural lower bits of the instruction address, said buffer controller circuit storing each of instructions having addresses in the range from the address immediately following the one of the instruction fetched to the final instruction address expressed by said plural lower bits into respective instruction buffer each corresponding to an instruction address of said plurality of instruction buffers, and setting flags each corresponding to respective instruction buffer to first state,
• said buffer controller circuit outputting to said instruction execution unit the instructions stored in the instruction buffers in response to the request of instruction fetch from said instruction execution unit, under the condition that the flags each associated with an instruction buffer corresponding to a value of said plural lower bits of the instruction address output by the instruction execution unit of the instruction to be fetched is set to the first state, and setting the flag to second state.

A data processor comprising:

• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• and
• a bus controller which controls access to an external bus in response to a command from said instruction execution unit,
• said bus controller having a plurality of instruction buffers, a flag specific to each of instruction buffers, and a buffer controller circuit;
• said buffer controller circuit being served for allocating to each of said instruction buffers one of specific values that plural lower bits of an instruction address may take, prefetching instructions to the instruction buffers each corresponding to a respective addresses designated to by said plural lower bits, from the address following a predetermined fetch address, setting the appropriate flag to valid in correspondence with the instruction prefetch, and setting the appropriate flag to invalid in response to the output of instructions prefetched to allow the number of instruction buffers for instructions to be prefetched among said plurality of instruction buffers to be variable.

A data processor, comprising:

• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• a bus controller which controls access to an external bus in response to the direction by said instruction execution unit;
• and
• an interrupt controller,
• said bus controller having a plurality of instruction buffers, a flag specific to each of instruction buffers, and a buffer controller circuit;
• said buffer controller circuit being served for allocating to each of said instruction buffers one of specific values that plural lower bits of an instruction address may take, prefetching instructions to the instruction buffers each corresponding to a respective addresses designated to by said plural lower bits, from the address following a predetermined fetch address, setting the appropriate flag to valid in correspondence with the instruction prefetch, and setting the appropriate flag to invalid in response to the output of instructions prefetched;
• wherein instruction prefetch to said instruction buffers may be suspended in response to reception of an interrupt by said interrupt controller.

A data processor, comprising:

• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• and
• a bus controller which controls access to an external bus in response to a command from said instruction execution unit,
• said bus controller including a first buffer table, a second buffer table, and a buffer controller circuit;
• each buffer table including a plurality of instruction buffers and a flag specific to each of instruction buffers;
• said buffer controller circuit being served for allocating to each of said instruction buffers included in each of said buffer tables one of specific values that plural lower bits of an instruction address may take, prefetching instructions to the instruction buffers each corresponding to a respective addresses designated to by said plural lower bits, from the address following a predetermined fetch address, setting the appropriate flag to valid in correspondence with the instruction prefetch, and setting the appropriate flag to invalid in response to the output of instructions prefetched;
• said buffer controller circuit outputting the instructions prefetched in said instruction buffers included in said second buffer table in response to the output of instructions prefetches in all of instruction buffers included in said first buffer table.

A data processor, comprising

• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• and
• a bus controller which controls access to an external bus in response to a command from said instruction execution unit,
• said bus controller having a plurality of instruction buffers, a flag specific to each of instruction buffers, a buffer controller circuit, and an instruction decoder unit;
• said buffer controller circuit being served for allocating to each of said instruction buffers one of specific values that plural lower bits of an instruction address may take, prefetching instructions to the instruction buffers each corresponding to a respective addresses designated to by said plural lower bits, from the address following a predetermined fetch address, setting the appropriate flag to valid in correspondence with the instruction prefetch, and setting the appropriate flag to invalid in response to the output of instructions prefetched;
• said instruction decoder unit decoding instructions to be stored in said instruction buffers;
• said bus controller suspending instruction prefetch if the instruction decoded belongs to a first type of instruction until said instruction will be output from said instruction buffers.

A data processor, comprising:

• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• and
• a bus controller which controls access to an external bus in response to a command from said instruction execution unit,
• said bus controller having a plurality of instruction buffers, a flag specific to each of instruction buffers, one or more of data buffers, a flag specific to each of said data buffers, an instruction decoder unit, an address calculator unit, and a buffer controller circuit;
• said buffer controller circuit being served for allocating to each of said instruction buffers one of specific values that plural lower bits of an instruction address may take, prefetching instructions to the instruction buffers each corresponding to a respective addresses designated to by said plural lower bits, from the address following a predetermined fetch address, setting the appropriate flag to valid in correspondence with the instruction prefetch, and setting the appropriate flag to invalid in response to the output of instructions prefetched;
• said instruction decoder unit decoding instructions to be stored in said instruction buffers;
• said address calculator calculating a predetermined address if the instruction in question is an instruction belonging to a second type of instruction that requires information for storing in said predetermined address, storing data stored in said predetermined address into said data buffer, setting the specific flag associated with said data buffer to valid, and setting the specific flag to invalid in response to the output of stored data.

A data processor, wherein:

• an instruction execution unit which fetches instructions, decodes thus fetched instructions, and executes thus fetched and decoded instructions;
• a bus controller which controls access to an external bus in response to a command from said instruction execution unit;
• and
• a cache memory,
• said bus controller having a plurality of instruction buffers, and a buffer controller circuit;
• said buffer controller circuit prefetching instructions into said instruction buffers, starting from the address succeeding to a predetermined address of instruction to be fetched;
• said instruction prefetched being equally supplied to said cache memory.