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AssigneeIntel Corporation
InventorsSiva Venkatraman, Earle F. Philhower III, Ruban Kanapathippillai, Manoj Mehta
Estimating the term…
A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.
A method in a memory having a bad memory cell, the method comprising:
A reconfigurable memory comprising:
An integrated circuit comprising:
A method of conserving power in an integrated circuit having parallel data buses, the method comprising:
Dependencies are inferred from the claim text.