Partial match partial output cache for computer arithmetic operations
AssigneeSamsung Electronics Co., Ltd.
InventorHoi-Jin Lee
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Abstract
An arithmetic device having a cache for performing arithmetic operations is provided. The cache stores previously performed resultant data and operand for an arithmetic operation and upon receiving a same operand to be operated upon, the corresponding stored resultant data is output, bypassing the arithmetic processing and operation by the processor. The device having the cache is also configured for outputting a partial resultant output for a partially matched operand.
Claims9
A method of performing arithmetic operation using a cache structure having a TAG register and a cache data memory, the method comprising the steps of:
- storing in the TAG register a plurality of known operands, each having a corresponding resultant derived from an arithmetic operation, the resultant being stored in a corresponding location in the cache data memory;
- inputting a new operand on which the arithmetic operation is to be performed to the TAG register;
- comparing the new operand to the plurality of the known operands;
- and
- determining if the new operand matches any of the known operands and if there is a match, outputting from the cache data memory the known resultant corresponding to the known operand that matched the new operand.
A cache device for performing arithmetic operation comprising:
- a tag register for storing a plurality of known operands, each having a corresponding resultant derived from an arithmetic operation;
- a cache data memory for storing resultants corresponding to the known operands;
- comparison logic in the tag register for comparing a new operand on, which the arithmetic operation is to be performed against the plurality of the known operands, wherein if the new operand matches any of the known operands, the cache data memory outputs the known resultant corresponding to the known operand that matched the new operand.
Dependencies are inferred from the claim text.