US 2002/0120811 A1Published application

Memory control device having less power consumption for backup

AssigneeCanon Kabushiki Kaisha

InventorTadaaki Maeda

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Abstract

When power stoppage of a main power supply is detected during a normal operation, a power controller switches a power supply for a DRAM from the main power supply to a battery power supply and makes an instruction signal for instruction a self-refresh mode to a memory controller active. In response to this, the memory controller changes a clock enable signal for the DRAM to a low level to establish the self-refresh mode of the DRAM, and, after, the self-refresh mode of the DRAM is established, supplying of power to the memory controller is stopped. The clock enable signal for the DRAM is maintained to the low level by pull-down resistance even when the supplying of power to the memory controller is stopped from a condition that the signal is changed to the low level in the self-refresh mode, thereby maintaining the self-refresh mode of the DRAM.

Claims10

Dependent claims

A memory control device comprising:

a memory controller for controlling an operation of a DRAM and for outputting a clock enable signal to said DRAM;
a power controller for controlling supplying of power to said DRAM from a main power supply or a back-up battery power supply and for detecting power stoppage of said main power supply;
and
pull-down resistance for pulling down the clock enable signal to low level;
and wherein
if said power controller detects the power stoppage of said main power supply during a normal operation, said power controller switches a power supply for said DRAM from said main power supply to said battery power supply and instructs a self-refresh mode to said memory controller, so that said memory controller changes the clock enable signal for said DRAM to the low level to establish the self-refresh mode of said DRAM, and
after said DRAM is set to the self-refresh mode, the supplying of power to said memory controller is stopped, and, even after the stoppage, the clock enable signal is maintained to the low level by said pull-down resistance, thereby maintaining the self-refresh mode.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/078,396Filed 21 Feb 2002
Priority: JP 047504-200123 Feb 2001
Published: 29 Aug 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 1/3275
Power saving in peripheral device: power saving in memory, e.g. RAM, cache
G06F 1/30
Power supply means, e.g. regulation thereof: means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
G06F 1/3203
Means for saving power: power management, i.e. event-based initiation of a power-saving mode
G06F 13/1668
For access to memory bus: details of memory controller