Link bus for a hub based computer architecture
AssigneeMicron Technology, Inc.
InventorA. Kent Porterfield
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorA. Kent Porterfield
Estimating the term…
A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The satellite devices are also connected to industry standard buses/devices and the central hub also communicates with a processor cluster and system memory over respective processor and memory buses. Thus, all components within the system are capable of communicating with each other through the hub. By communicating over the link buses via the link bus protocol, satellite devices can report events to other devices without dedicated wiring/pins between the devices as is currently performed in the prior art. In addition, the flushing of data buffers is governed by the protocol such that only targeted data buffers are flushed, which improves overall system performance.
A method of operating a processor based system, the system comprising a hub coupled to a processor by a processor bus and coupled to a memory device by a memory bus, said hub being connected to a first device by a first link bus, the first device communicating with the at least one processor and the memory device via the hub, said method comprising the steps of:
A method of operating a hub based processor system, the system comprising a link hub connected to a first satellite device by a first link bus, the link hub being connected to a processor via a processor bus and a memory device via a memory bus, said method comprising the steps of:
A processor system comprising:
A processor based system comprising:
A processor based system comprising:
Dependencies are inferred from the claim text.