Technique for capturing information
AssigneeIntel Corporation
InventorsJoseph A. Bennett, Blaise B. Fanning
Life of this patent
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Abstract
An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected to at least one processor to control a memory in response to instructions from the at least one processor. An I/O controller is connected to the memory controller to control data flow to at least one device in response to instructions from the at least one processor. Lock down logic stores captured cycle information on a processor cycle that results in interrupt.
Claims30
An information capturing apparatus to capture cycle information on a processor cycle that results in a high level interrupt comprising:
- a memory controller connected to at least one processor to control a memory in response to instructions from said at least one processor;
- an I/O controller connected to said memory controller to control data flow to at least one device in response to instructions from said at least one processor;
- and
- lock down logic to store captured cycle information on a processor cycle that results in an interrupt.
A method of capturing cycle information on a processor cycle that results in a high level interrupt, the method comprising:
- decoding instructions from a least one processor to decode an interrupt;
- outputting an interrupt signal to the at least one processor in response to the decoded interrupt;
- and
- capturing and storing cycle information on a processor cycle that results in interrupt.
A method of capturing cycle information on a processor cycle that results in a higher level interrupt in a system including at least one processor and a memory controller and an I/O controller, the method comprising:
- controlling a memory with the memory controller in response to instructions from the at least one processor;
- controlling data flow to at least one device with the I/O controller in response to instructions from the at least one processor;
- and
- storing captured cycle information on a processor cycle that results in an interrupt.
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method of capturing cycle information on a processor cycle that results in a high level interrupt, the method comprising:
- decoding instructions from a least one processor to decode an interrupt;
- outputting an interrupt signal to the at least one processor in response to the decoded interrupt;
- and
- capturing and storing cycle information on a processor cycle that results in interrupt.
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method of capturing cycle information on a processor cycle that results in a higher level interrupt in a system including at least one processor and a memory controller and an I/O controller, the method comprising:
- controlling a memory with the memory controller in response to instructions from the at least one processor;
- controlling data flow to at least one device with the I/O controller in response to instructions from the at least one processor;
- and
- storing captured cycle information on a processor cycle that results in an interrupt.
Dependencies are inferred from the claim text.