Method and system to promote arbitration priority in a buffer queue
AssigneeHewlett-Packard Development Company, L.P.
InventorParas A. Shah
Life of this patent
Estimating the term…
Abstract
A technique is provided for prioritizing access to a bus for read completion transactions. The technique incorporates logic within an ASIC bridge, wherein split completion transactions are designated a priority level that facilitates the delivery of the requested data to a periphery device. Particularly, logic within the ASIC grants a read completion transaction a level one priority designation, which provides access to the bus to a requesting device prior to devices designated with a level two priority designation.
Claims23
A method for arbitrating access to a bus between a bridge and a device coupled to the bus, wherein at least either the bridge or the device may be granted a level one priority designation or a level two priority designation, wherein the level one priority designation permits access to the bus before the level two priority designation comprising the acts of:
- a) determining whether a transaction is a split completion transaction;
- b) if the transaction is a split completion transaction, granting the level one priority designation to the bridge;
- and
- c) if the transaction is not a split request transaction, granting the level two priority designation to the bridge.
A system for arbitrating access to a bus between a bridge and a device coupled to the bus, wherein at least one of the bridge and the device may be granted a level one priority designation or a level two priority designation, wherein a level one priority designation permits access to the bus before the level two priority designation comprising:
- means for determining whether a transaction is a split completion transaction;
- means for granting the level one priority designation to the bridge, if the transaction is a split completion transaction;
- and
- means for granting the level two priority designation to the bridge, if the transaction is not a split completion transaction.
A computer system comprising:
- at least one processor;
- a bridge operatively coupled to the at least one processor;
- a bus operatively coupled to the bridge and to a plurality of peripheral devices;
- and
- an arbiter logic device configured to arbitrate access to the bus between the bridge and the plurality of peripheral devices, wherein at least one of the bridge and the plurality of peripheral devices may be granted a level one priority designation or a level two priority designation, wherein a level one priority designation.
Dependencies are inferred from the claim text.