Die testing using top surface test pads
AssigneeTexas Instruments Incorporated
InventorsLee D. Whetsel, Richard L. Antley
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Abstract
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
Claims9
A process of fabricating die comprising the steps of;
- processing at least one die on a semiconductor wafer,
- providing pads at the periphery of the die for communicating functional signals, and;
- providing pads on the top surface of the die for communicating test signals.
A process of fabricating die comprising the steps of;
- processing at least one die on a semiconductor wafer,
- providing pads at the periphery of the die for making contact to voltages required to operate the die functionally, and
- providing pads on the top surface of the die for providing contact to voltages required to operate the die in a test mode.
A process of probing a die on wafer to connect a tester to the die comprising the steps of;
- probing pads located on the periphery of die,
- probing pads located on the top surface of the die, and
- operating the tester to communicate test signals to and from the die by way of said periphery and top surface pads.
A process of fabricating die on a semiconductor wafer comprising the steps of;
- processing at least one die on said wafer, said die including at least one embedded core circuit having input terminals and output terminals,
- providing pads on the periphery of the die, at least one of said periphery pads being connected to one of an input terminal and output terminal;
- and,
- providing pads on the top surface of the die, at least one of said top surface pads being connected to at least another one of an input terminal and output terminal.
A process of testing and packaging a die comprising the steps of;
- processing a first group of pads on the top surface of the die for communicating test signals to and from the die,
- processing a second group of pads on the periphery of the die for communicating functional signals to and from the die;
- testing the die using the first group of pads, and
- bonding the die to a lead frame using the second group of pads.
A process of testing and mounting a die comprising the steps of;
- processing a first group of pads on the top surface of the die for communicating test signals to and from the die,
- processing a second group of pads on the periphery of the die for communicating functional signals to and from the die;
- testing the die using the first group of pads, and
- mounting the die on a substrate using the second group of pads.
A process of fabricating a die comprising the steps of;
- processing at least one die on a semiconductor wafer,
- processing a first group of pads on the top surface of the die for communicating signals to and from the die,
- processing a second group of pads on the periphery of the die for communicating signals to and from the die;
- testing the die using the first and second groups of pad, and
- processing an insulating layer over the first group of pads, but not over the second group of pads.
An integrated circuit die comprising;
- functional die pads located at the periphery of said die,
- test pads located on to top surface of said die,
- at least one embedded circuit core having input terminals and output terminals,
- at least one connection selectively formed between at least one of said test pads and one of an input terminal and output terminal of said circuit core.
An integrated circuit die comprising;
- functional die pads located at the periphery of said die,
- test pads located on to top surface of said die,
- at least one embedded circuit core having input terminals and output terminals,
- a first connection formed between one of said test pads and one of an input terminal and output terminal of said circuit core, and
- a second connection formed between one of said functional pads and one of an input terminal and output terminal of said circuit core.
Dependencies are inferred from the claim text.