US 2002/0119632 A1Published application

Dual salicidation process

AssigneeVanguard International Semiconductor Corporation

InventorHorng-Huei Tseng

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Abstract

A dual salicidation process is used on a semiconductor substrate which has a gate dielectric, a polysilicon gate conductor patterned upon a predetermined area of the gate dielectric, a sacrificial layer patterned upon the polysilicon gate conductor, and LDD areas formed within the substrate at opposed sidewall of the polysilicon gate conductor. First, an insulator spacer on the sidewall of the polysilicon gate conductor and the sacrificial layer, and then the gate dielectric not covered by the insulator spacer is removed. Next, source/drain regions are formed within the substrate at the outer lateral surfaces of the insulator spacer. Thereafter, using salicidation process, silicide structures are formed upon the source/drain regions. After removing the sacrificial layer salicidation process is used again to convert the polysilicon gate conductor into a silicide gate conductor.

Claims26

Dependent claims

A dual salicidation process, comprising the steps of:

(a) providing a semiconductor substrate which comprises a gate dielectric, a polysilicon gate conductor patterned upon a predetermined area of the gate dielectric, a sacrificial layer patterned upon the polysilicon gate conductor, and LDD areas formed within the substrate at opposed sidewall of the polysilicon gate conductor;
(b) performing a thermal oxidization process to form a poly-oxide spacer on the sidewall of the polysilicon gate conductor;
(c) performing an implantation process to form source/drain regions within the substrate at the outer lateral surfaces of the poly-oxide spacer;
(d) removing the sacrificial layer;
(e) depositing a first layer of refractory metal across exposed surfaces of the gate dielectric, the poly-oxide spacer, and the polysilicon gate conductor;
(f) heating the first layer of refractory metal to convert the polysilicon gate conductor to a silicide gate conductor,
(g) removing the first layer of refractory metal which is not reacted;
(h) removing the gate dielectric from the source/drain regions;
(i) depositing a second layer of refractory metal across the source/drain regions, the poly-oxide spacer, and the silicide gate conductor;
(j) heating the second layer of refractory metal to form silicide structures upon the source/drain regions;
and
(k) removing the second layer of refractory metal which is not reacted.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/051,075Filed 22 Jan 2002
Priority: TW 9010622016 Mar 2001
Published: 29 Aug 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 30/0213
Using self-aligned silicidation: providing different silicide thicknesses on gate electrodes and on source regions or drain regions
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 64/0112
To Group IV semiconductors: using conductive layers comprising silicides

Family

Application09/790,513Continuation in part · filed 23 Feb 2001
Application10/051,075Continuation in part · filed 22 Jan 2002
US 2002/0119631 A1Published application
US 6,524,939 B2Related patent
US 6,528,402 B2Related patent
US 2002/0119632 A1This patent

From the US filing history. Foreign family members aren’t listed.