STI method for semiconductor processes

A shallow trench isolation (STI) process having a reduced Kooi effect, the process comprising:

• providing a substrate;
• forming a pad oxide layer on the substrate;
• forming a silicon layer on the pad oxide layer;
• forming a resist layer on the silicon layer, wherein the resist layer has at least one opening exposing portions of the underlying silicon layer;
• performing a first dry etching process to etch away the silicon layer, pad oxide layer, and the substrate through the opening, thereby forming a trench in the substrate;
• removing the resist layer;
• performing an oxidation process to simultaneously form a liner on an interior surface of the trench and an oxide layer with a predetermined thickness on the silicon layer;
• depositing an insulating layer on the oxide layer and the liner and filling the trench;
• performing a chemical mechanical polishing (CMP) process to polish the insulating layer and the oxide layer atop the silicon layer, thereby exposing the silicon layer and the remaining oxide layer to protect STI corner regions;
• and
• performing a second dry etching process to remove the silicon layer.